From 7de57abe978945469859a64d095973c0c97be147 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Jan 2024 18:33:10 +0000 Subject: [PATCH] bug 1034: properly qualify crbinlog and crternlogi in sv_analysys.py --- openpower/isatables/RM-1P-2S1D.csv | 2 ++ openpower/isatables/RM-1P-3S1D.csv | 1 + src/openpower/decoder/power_svp64.py | 4 +++- src/openpower/sv/sv_analysis.py | 6 +++++- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index a9fc8956..79f1952a 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -7,6 +7,8 @@ crand,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 creqv,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 crorc,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 cror,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 +crbinlog,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 +crternlogi,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 cmp,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 cmpl,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 cmprb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index 689caa56..0c6a8f74 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -31,6 +31,7 @@ isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 +binlog,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddhd,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddhdu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddedu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index 97463b6a..cfa33805 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -156,9 +156,11 @@ class SVP64RM: index2 = svp64_src.get('BB', None) entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2) elif cr_in == 'BFA_BFB_BF': + # three indices but one is a source *and* destination + # BF is marked as a dest but is actually also src index1 = svp64_src.get('BFA', None) index2 = svp64_src.get('BFB', None) - index3 = svp64_src.get('BF', None) + index3 = svp64_dest.get('BF', None) # read-modify-write entry['sv_cr_in'] = "Idx_%d_%d_%d" % (index1, index2, index3) # CRout a lot easier. ignore WHOLE_REG for now diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 21778ad0..b0e2ae4a 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -546,7 +546,11 @@ def extra_classifier(insn_name, value, name, res, regs): elif value == 'RM-1P-2S1D': res['Etype'] = 'EXTRA3' # RM EXTRA3 type - if insn_name.startswith('cr'): + if insn_name in ['crbinlog', 'crternlogi']: + res['0'] = 'd:BF' # BF: Rdest1_EXTRA3 + res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3 + res['2'] = 's:BFB' # BFB: Rsrc2_EXTRA3 + elif insn_name.startswith('cr'): res['0'] = 'd:BT' # BT: Rdest1_EXTRA3 res['1'] = 's:BA' # BA: Rsrc1_EXTRA3 res['2'] = 's:BB' # BB: Rsrc2_EXTRA3 -- 2.30.2