From c010a1557aba5e1f9dc004c1ad9ec2cb26eabcfd Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 1 Feb 2017 13:53:54 -0800
Subject: [PATCH] sifive-blocks: trust diplomacy to get names right

---
 src/main/scala/devices/pwm/PWMPeriphery.scala   | 6 +++---
 src/main/scala/devices/spi/SPIPeriphery.scala   | 6 +++---
 src/main/scala/devices/uart/UARTPeriphery.scala | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 992699f..86e9ad2 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -30,8 +30,8 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
 trait PeripheryPWM {
   this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
 
-  val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
-    val pwm = LazyModule(new TLPWM(c) { override lazy val  valName = Some(s"pwm$i") })
+  val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
+    val pwm = LazyModule(new TLPWM(c))
     pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := pwm.intnode
     pwm
@@ -52,7 +52,7 @@ trait PeripheryPWMModule {
     val outer: PeripheryPWM
     val io: PeripheryPWMBundle
   } =>
-  (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
+  (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
     io.port := device.module.io.gpio
   }
 }
diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec6..f4773a2 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
 
 trait PeripherySPI {
   this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
+  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+    val spi = LazyModule(new TLSPI(c))
     spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := spi.intnode
     spi
@@ -28,7 +28,7 @@ trait PeripherySPIModule {
     val outer: PeripherySPI
     val io: PeripherySPIBundle
   } =>
-  (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+  (io.spis zip outer.spi).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35..3639d9b 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -14,8 +14,8 @@ trait PeripheryUART {
   this: TopNetwork {
     val uartConfigs: Seq[UARTConfig]
   } =>
-  val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
-    val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
+  val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+    val uart = LazyModule(new UART(c))
     uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := uart.intnode
     uart
@@ -32,7 +32,7 @@ trait PeripheryUARTModule {
     val outer: PeripheryUART
     val io: PeripheryUARTBundle
   } =>
-  (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
+  (io.uarts zip outer.uart).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
-- 
2.30.2