From c6150d05867bea1a7266e3c950d3d9846ba7ed58 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 6 Nov 2020 01:31:14 +0000 Subject: [PATCH] vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires. These only matter in simulation and after conversion to Verilog. During synthesis they cause Yosys to produce warnings: Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute. --- nmigen/vendor/lattice_ecp5.py | 1 + nmigen/vendor/lattice_ice40.py | 1 + 2 files changed, 2 insertions(+) diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index 3affa8f..2a68dad 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -122,6 +122,7 @@ class LatticeECP5Platform(TemplatedPlatform): read_ilang {{file}} {% endfor %} read_ilang {{name}}.il + delete w:$verilog_initial_trigger {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}} {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}} diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index d5e4dd6..4e6b282 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -124,6 +124,7 @@ class LatticeICE40Platform(TemplatedPlatform): read_ilang {{file}} {% endfor %} read_ilang {{name}}.il + delete w:$verilog_initial_trigger {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} synth_ice40 {{get_override("synth_opts")|options}} -top {{name}} {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}} -- 2.30.2