From ea854f5da7c0a68b26395f22cebd9e8eb22fa435 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 30 Apr 2022 22:20:02 +0100
Subject: [PATCH] add missing module

---
 src/soc/fu/div/pipeline.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index 7fbbf10c..6fc01a50 100644
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -84,5 +84,6 @@ class DivBasePipe(ControlBase):
             name = f"pipe_middle_{i}"
             setattr(m.submodules, name, self.pipe_middles[i])
         m.submodules.pipe_end = self.pipe_end
+        m.submodules.pipe_final = self.pipe_final
         m.d.comb += self._eqs
         return m
-- 
2.30.2