From eabef61d80f41a8f8051b7bb32749a93df708d7a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 3 Feb 2024 08:20:18 +0000 Subject: [PATCH] sigh, when maddsubrs (etc) moved to PO5, PowerDecoder2 hack update --- src/openpower/decoder/isa/caller.py | 10 ++++++---- src/openpower/decoder/power_decoder2.py | 10 +++++----- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 9234c300..d4f59a31 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -634,6 +634,9 @@ def get_out_map(dec2, name): if name == 'RA': if out_sel == OutSel.RA.value: return True + elif name == 'RS': + if out_sel == OutSel.RS.value: + return True elif name == 'RT': if out_sel == OutSel.RT.value: return True @@ -696,14 +699,12 @@ def get_out2_map(dec2, name): if name == 'RS': fft_en = yield dec2.implicit_rs if fft_en: - log("get_idx_out2", out_sel, OutSel.RS.value, - out) + log("get_idx_out2", out_sel, OutSel.RS.value, out) return True if name == 'FRS': fft_en = yield dec2.implicit_rs if fft_en: - log("get_idx_out2", out_sel, OutSel.FRS.value, - out) + log("get_idx_out2", out_sel, OutSel.FRS.value, out) return True return False @@ -723,6 +724,7 @@ def get_idx_out2(dec2, name, ewmode=False): if ismap: log("get_idx_out2", name, out_sel, out, o_isvec) return out, o_isvec + log("get_idx_out2 not found", name, out_sel, out, o_isvec) return None, False diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 9e3bca4a..d216c1c7 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1082,11 +1082,11 @@ class PowerDecodeSubset(Elaboratable): )): comb += self.implicit_rs.eq(1) comb += self.extend_rc_maxvl.eq(1) # RS=RT+MAXVL or RS=RC - # implicit RS for major 22, integer maddsubrs - with m.If((major == 22) & xo6.matches( - '-01000', # maddsubrs - '-01001', # maddrs - '-01011', # msubrs + # implicit RS for major 5, integer maddsubrs + with m.If((major == 5) & xo6.matches( + '100100', # maddsubrs + '101100', # maddrs + '110100', # msubrs )): comb += self.implicit_rs.eq(1) comb += self.extend_rb_maxvl.eq(1) # extend RB -- 2.30.2