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cpu: Base dyn inst HTM flags getter
2020-09-08 Timothy Hayescpu: Base dyn inst HTM flags getter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-08 Timothy Hayessim: Add HTM Generic Fault
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-08 Timothy Hayescpu: Add HTM ThreadContext API
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-08 Timothy Hayescpu: Add HTM ExecContext API
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-07 Timothy Hayesmem: Add HTM fields to Request
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-07 Timothy Hayescpu: Add HTM CPU API
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-07 Timothy Hayescpu: Add HTM Instruction Flags
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-07 Timothy Hayescpu: Add HtmCpu DebugFlag
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2020-09-02 Timothy Hayesmem: Relax packet limit in packet queue
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-02 Timothy Hayesarch: Add uReset helper to UPCState
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-02 Timothy Hayesarch, mem: Initial Hardware Transactional Memory implementation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Fix coding style in addressTranslation methods
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Check if PAC is implemented before executing...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Introduce HavePACExt helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Rewrite addressTranslation to use BitUnions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Remove deadcode from AArch64 address translation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Refactor Address Translation (AT) code
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Early checking if debug is enabled in TLB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Rename SelfDebug member variables
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Remove setters from SoftwareStep
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Add Xen compilation to gen_arm_fs_files.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Remove dependency check
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Allow the short -j option in gen_arm_fs_files.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Change gen_arm_fs_files.py to allow selective...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Use isSecure variable for Stage2Lookup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix physmem NS attribute in VMSAv8-32 descriptors
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: VSTTBR_EL2 doesn't contain a VMID field
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Disable HVC when SCR_EL3.HCE is 0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix XN in TLB permissions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix SoftwareStep::debugExceptionReturnSS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-10 Giacomo Travagliniarch-arm: Reduce boilerplate when extracting SelfDebug...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-10 Giacomo Travaglinidev-arm: Fix <timer>_CTL_EL<x>.ISTATUS when masking...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Avoid code duplication in Pl111
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Relax size constraint on AMBA ID registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Fix DTB autogen for HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make the Sp805 use the new ArmInterruptPin...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Sp804 use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Pl011 UART use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Introduce the active boolean for ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive PPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive SPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Gicv3 maintenance interrupt never cleared
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Check for security attribute when writing...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Remove SPI/PPI range check in Gicv3 class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-15 Giacomo Travagliniarch-arm: AddressSize check on translateMmuOff for...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Fix coding style in self_debug.[cc, hh]
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Remove getters/setters from SelfDebug class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Fix pmc == on SelfDebug
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Move breakpoint/watchpoint check out of the TLB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Style fixes for src/dev/arm/gic_v2.hh
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Implement Level Sensitive PPIs in GICv2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Use getIntConfig when reading/writing GICD_ICFGR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Move GICv2 intConfig for consistency
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-07 Michiel W. van Tolcpu-o3: Avoid passing ReExec 'faults' on CPU tracing...
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2020-06-26 Giacomo Travagliniext: Remove dead code from results.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-26 Giacomo Travagliniext: Remove dead code from main.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-26 Giacomo Travagliniext: Remove dead code from configuration.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-25 Giacomo Travaglinisim: Fix -Werror=maybe-uninitialized in system.cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-25 Giacomo Travagliniarch-arm: Fix arm switcheroo regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-22 Michiel W. van Tolcpu: Use new InstRecord faulting flag in cpu models
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2020-06-22 Michiel W. van Tolsim: Add faulting flag to instruction tracing interface
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2020-06-22 Giacomo Travagliniscons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-19 Michiel W. van Tolarch-arm: Add missing isFirstMicroop flags on uop sequences
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2020-06-18 Giacomo Travagliniext: Remove dead code from runner.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from handlers.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from fixture.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from loader.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from helper.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from test_util.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove LogWrapper/TestLogWrapper from log.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Fix the MakeFixture setup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Avoid specifying empty interfaces and embrace...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove sandbox module from testlib
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travaglinitests: log_call is not returning any value
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-14 Giacomo Travaglinitests: Use default None argument in makeArmSystem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-08 Giacomo Travaglinimisc: Remove any reference to the ALPHA ISA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-20 Michiel W. van Tolpython: Make DOT config generation optional
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2020-05-14 Giacomo Travaglinimisc: Add Arm contributions to gem5-20 RELEASE-NOTES.md
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-12 Jason Lowe-Powerscons: Update python-config flags for python3.8
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2020-05-12 Giacomo Travagliniscons: Add readCommandWithReturn helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-11 Timothy Hayesmem-ruby: MESI_Two_Level missing function compilation fix
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2020-05-11 Timothy Hayesmem-ruby: MOESI_CMP_directory sync fix
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2020-05-09 Giacomo Travagliniarch-arm: SVE instruction in EL1s cannot be trapped...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: CPTR.FPEN controlling SVE enablement
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: Remove checkSveTrap method
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travaglinipython: Manually convert float to int when using %x
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Make cpt_upgraders python3 compatible
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Port git hooks to python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-04 Giacomo Travagliniarch-arm: Decode SEVL instruction for A32 and T32 IS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travagliniconfigs: Do not require args.kernel to be set in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travaglinisim, arch-arm: Restore capability of running without...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: SVE instructions do not use AHP format
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: Do not increment exponent if FPSCR.FZ in...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Use workloads.py in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Produce list of workload types in workloads.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Add an example workloads module
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --machine-type option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --semi-path option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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