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Stray dump
2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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2019-09-26
Eddie Hung
mul2dsp.v slice names
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2019-09-26
Eddie Hung
Do not die if DSP48E1.P has no users (would otherwise...
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2019-09-26
Eddie Hung
Reject if (* init *) present
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2019-09-26
Eddie Hung
Remove unnecessary check for A_SIGNED != B_SIGNED;...
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2019-09-26
Eddie Hung
Revert "Remove _TECHMAP_CELLTYPE_ check since all ...
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2019-09-26
Eddie Hung
Revert "No need for $__mul anymore?"
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2019-09-26
Eddie Hung
Rework xilinx_dsp postAdd for new wreduce call
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2019-09-26
Eddie Hung
Only wreduce on t:$add
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2019-09-25
Eddie Hung
Remove _TECHMAP_CELLTYPE_ check since all $mul
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2019-09-25
Eddie Hung
Fix memory issue since SigSpec& could be invalidated
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2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar...
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2019-09-25
Eddie Hung
No need for $__mul anymore?
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2019-09-25
Eddie Hung
unextend only used in init
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2019-09-25
Eddie Hung
Call 'wreduce' after mul2dsp to avoid unextend()
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2019-09-25
Eddie Hung
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
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2019-09-24
Eddie Hung
Add (* techmap_autopurge *) to abc_unmap.v too
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2019-09-24
Eddie Hung
"abc_padding" attr for blackbox outputs that were padded...
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2019-09-24
Eddie Hung
Force $inout.out ports to begin with '$' to indicate...
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2019-09-24
Eddie Hung
Add techmap_autopurge to outputs in abc_map.v too
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2019-09-24
Eddie Hung
Revert "Add a xilinx_finalise pass"
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2019-09-24
Eddie Hung
Revert "Remove (* techmap_autopurge *) from abc_unmap...
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2019-09-24
Eddie Hung
Revert "Vivado does not like zero width port connections"
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2019-09-24
Eddie Hung
Vivado does not like zero width port connections
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2019-09-24
Eddie Hung
Remove (* techmap_autopurge *) from abc_unmap.v since...
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2019-09-24
Eddie Hung
Add a xilinx_finalise pass
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2019-09-23
Eddie Hung
Set [AB]CASCREG to legal values
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2019-09-23
Eddie Hung
Comment to explain separating CREG packing
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2019-09-23
Eddie Hung
Separate out CREG packing into new pattern, to avoid...
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2019-09-23
Eddie Hung
Move log_debug("\n") later
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2019-09-23
Eddie Hung
Move unextend initialisation later
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2019-09-23
Eddie Hung
Use new port() overload once more
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2019-09-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-21
Eddie Hung
Hell let's add the original #1381 testcase too
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2019-09-21
Eddie Hung
Revert abc9.cc
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2019-09-21
Eddie Hung
Add testcase
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2019-09-21
Eddie Hung
Trim mismatched connection to be same (smallest) size
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2019-09-21
Eddie Hung
Fix first testcase in #1391
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2019-09-20
Eddie Hung
Grammar
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2019-09-20
Eddie Hung
Use new port/param overload in pmg
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2019-09-20
Eddie Hung
Output pattern matcher items as log_debug()
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2019-09-20
Eddie Hung
OPMODE is port not param
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2019-09-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-20
Eddie Hung
Do not run xilinx_dsp_cascadeAB for now
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2019-09-20
Eddie Hung
WIP for xiinx_dsp_cascadeAB
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2019-09-20
Eddie Hung
Run until convergence
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2019-09-20
Eddie Hung
Cleanup ice40_dsp.pmg
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2019-09-20
Eddie Hung
Cleanup xilinx_dsp
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2019-09-20
Eddie Hung
More exceptions
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2019-09-20
Eddie Hung
Fix signedness bug
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2019-09-20
Eddie Hung
Update doc
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2019-09-20
Eddie Hung
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
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2019-09-20
Eddie Hung
Add an overload for port/param with default value
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2019-09-20
Eddie Hung
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
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2019-09-20
Eddie Hung
Revert "Move mul2dsp before wreduce"
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2019-09-20
Eddie Hung
Move mul2dsp before wreduce
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2019-09-20
Eddie Hung
Small cleanup
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2019-09-20
Eddie Hung
Disable support for SB_MAC16 reset since it is async
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2019-09-20
Eddie Hung
SB_MAC16 ffCD to not pack same as ffO
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2019-09-20
Eddie Hung
Add more complicated macc testcase
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2019-09-20
Eddie Hung
Clarify
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2019-09-20
Eddie Hung
Update doc for ice40_dsp
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2019-09-20
Eddie Hung
Tidy up, fix undriven
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2019-09-20
Eddie Hung
Add an index
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2019-09-20
Eddie Hung
$__ABC_REG to have WIDTH parameter
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2019-09-20
Eddie Hung
Fix DSP48E1 timing by breaking P path if MREG or PREG
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2019-09-20
Eddie Hung
Revert "Different approach to timing"
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2019-09-20
Eddie Hung
Different approach to timing
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2019-09-20
Eddie Hung
Fix width of D
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2019-09-20
Eddie Hung
Add mac.sh and macc_tb.v for testing
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2019-09-19
Eddie Hung
Suppress $anyseq warnings
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2019-09-19
Eddie Hung
Use ID() macro
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2019-09-19
Eddie Hung
Use (* techmap_autopurge *) to suppress techmap warnings
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2019-09-19
Eddie Hung
D is 25 bits not 24 bits wide
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2019-09-19
Eddie Hung
Merge remote-tracking branch 'origin/clifford/fix1381...
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2019-09-19
Eddie Hung
When two boxes connect to each other, need not be a...
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2019-09-19
Eddie Hung
Re-enable sign extension for C input
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2019-09-19
Eddie Hung
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB...
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2019-09-19
Eddie Hung
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
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2019-09-19
Eddie Hung
Do not perform width-checks for DSP48E1 which is much...
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2019-09-19
Eddie Hung
Remove TODO as check should not be necessary
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2019-09-19
Eddie Hung
Revert index to select
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2019-09-19
Eddie Hung
Cleanup xilinx_dsp too
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2019-09-19
Eddie Hung
Refactor ce{mux,pol} -> hold{mux,pol}
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2019-09-19
Eddie Hung
Add HOLD/RST support for SB_MAC16
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2019-09-19
Eddie Hung
Add support for SB_MAC16 CD and H registers
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2019-09-19
Eddie Hung
Refactor ice40_dsp.pmg
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2019-09-19
Eddie Hung
Add more entries
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2019-09-19
Eddie Hung
Format macc.v
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2019-09-19
Eddie Hung
Cleanup
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2019-09-18
Eddie Hung
Remove stat
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2019-09-18
Eddie Hung
Document (* gentb_skip *) attr for test_autotb
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2019-09-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-18
Eddie Hung
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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2019-09-18
Eddie Hung
Add doc on pattern detector for overflow
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2019-09-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-18
Eddie Hung
Fix copy-paste
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2019-09-18
Eddie Hung
Check overflow condition is power of 2 without using...
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2019-09-18
Eddie Hung
Add .gitignore
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2019-09-18
Eddie Hung
Refine macc testcase
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