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Add "synth_xilinx -arch"
2019-05-07 Clifford WolfAdd "synth_xilinx -arch"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-07 Clifford WolfMore opt_clean cleanups
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
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2019-05-06 Clifford WolfMerge pull request #975 from YosysHQ/clifford/fix968
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2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
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2019-05-06 Clifford WolfAdd tests/various/chparam.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-06 Clifford WolfFix the other bison warning in ilang_parser.y
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfBugfix in peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfMerge pull request #992 from bwidawsk/bison-fix
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2019-05-06 Clifford WolfMerge pull request #989 from YosysHQ/dave/abc_name_improve
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2019-05-06 Clifford WolfFix bug in "expose -input"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfCleanups in opt_clean
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfImprove tests/various/specify.ys
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfAdd "real" keyword to ilang format
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-04 Clifford WolfMerge pull request #988 from YosysHQ/clifford/fix987
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2019-05-04 Clifford WolfImprove opt_clean handling of unused wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 Clifford WolfAdd support for SVA "final" keyword
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 Clifford WolfImprove write_verilog specify support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 Clifford WolfUpdate README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 Clifford WolfAdd approximate support for SV "var" keyword, fixes...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfAdd "hierarchy -chparam" support for non-verific top...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
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2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
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2019-05-03 Clifford WolfMerge pull request #985 from YosysHQ/clifford/fix981
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2019-05-03 Clifford WolfFix typo in tests/svinterfaces/runone.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfMerge pull request #979 from jakobwenzel/svinterfacesTestcase
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2019-05-03 Clifford WolfImprove opt_expr and opt_clean handling of (partially...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfFurther improve unused-detection for opt_clean driver...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfImprove unused-detection for opt_clean driver-driver...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfUpdate pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 Clifford WolfFix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-02 Clifford WolfMerge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
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2019-05-01 Clifford WolfMerge branch 'clifford/fix883'
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2019-05-01 Clifford WolfAdd missing enable_undef to "sat -tempinduct-def",...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfMerge pull request #977 from ucb-bar/fixfirrtlmem
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2019-05-01 Clifford WolfFix floating point exception in qwp, fixes #923
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfAdd splitcmplxassign test case and silence splitcmplxassign...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfAdd additional test cases for for-loops
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfSilently resolve completely unused cell-vs-const driver...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 Clifford WolfRe-enable "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfFix segfault in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfDisabled "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
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2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
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2019-04-30 Clifford WolfMerge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
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2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
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2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
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2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfFix performance bug in RTLIL::SigSpec::operator==(...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfAdd final loop variable assignment when unrolling for...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfAdd handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfAdd peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford Wolfpmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfRun "peepopt" in generic "synth" pass and "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfSome pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 Clifford WolfProgress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 Clifford WolfMerge pull request #960 from YosysHQ/eddie/equiv_opt_undef
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2019-04-29 Clifford WolfMerge pull request #967 from olegendo/depfile_esc_spaces
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2019-04-29 Clifford WolfAdd "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 Clifford WolfAdd pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 Clifford WolfSupport multiple pmg files (right now just concatenated...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 Clifford WolfDrive dangling wires with init attr with their init...
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2019-04-23 Clifford WolfAdd specify support to README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfImprove $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfImprove $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfPreserve $specify[23] cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAllow $specify[23] cells in blackbox modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd $specify2/$specify3 support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd support for $assert/$assume/$cover to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd CellTypes support for $specify2 and $specify3
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd InternalCellChecker support for $specify2 and ...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfUn-break default specify parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd specify parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfAdd $specify2 and $specify3 cells to simlib
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 Clifford WolfMerge pull request #957 from YosysHQ/oai4fix
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2019-04-23 Clifford WolfRemove some left-over log_dump()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
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2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
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2019-04-22 Clifford WolfMerge pull request #949 from YosysHQ/clifford/pmux2shimprove
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2019-04-22 Clifford WolfMerge pull request #953 from YosysHQ/clifford/fix948
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2019-04-22 Clifford WolfAdd support for zero-width signals to Verilog back...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfDetermine correct signedness and expression width in...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfAdd log_debug() framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfMerge pull request #950 from whitequark/attrmap_remove_wildcard
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2019-04-22 Clifford WolfUpdaye pmux2shiftx test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfAdd full_pmux feature to pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfSet ENABLE_LIBYOSYS=0 by default
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfSet ENABLE_PYOSYS=0 by default
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
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2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22 Clifford WolfMerge branch 'dh73-master'
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2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_gowin...
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2019-04-22 Clifford WolfRe-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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