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dev-arm: pending SMMU transl update on constructor/destructor
2019-06-26 Adrian Herreradev-arm: pending SMMU transl update on constructor...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-20 Giacomo Travagliniconfigs: Fix NULL dram-lowp regressions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-17 Giacomo Travagliniarch-arm: Move the memacc_code before op_wb in fp loads
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-17 Giacomo Travaglinidev-arm: Reapply GICv3 changes that were lost during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-09 Giacomo Travaglinibase: Provide a getter for Fiber::started boolean variable
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-09 Giacomo Travaglinibase: Rename TestFiber into SwitchingFiber
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-07 Giacomo Travagliniarch-arm: Fix WalkerState,Descriptors default constructor
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-06-06 Stanislaw Czerniawskidev-arm: Implement a SMMUv3 model
- Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-24 Giacomo Travagliniarch-arm: Fix fallthrough when trapping at EL2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-23 Giacomo Travagliniarch-arm: Trap virtual accesses to GICv3 SGI registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-23 Giacomo Travagliniarch-arm: Expose haveGicv3CPUInterface to the ISA interface
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-23 Giacomo Travagliniarch-arm: Change mcrMrc15TrapToHyp signature
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-22 Giacomo Travaglinidev-arm: Provide a GICv3 ITS Implementation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-14 Giacomo TravagliniRevert "cpu: fix how a thread starts up in MinorCPU"
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-14 Giacomo TravagliniRevert "cpu: stop scheduling suspended threads in MinorCPU"
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-14 Giacomo TravagliniRevert "cpu: fix branching when thread is suspended...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-03 Giacomo Travaglinidev: StreamID generation in DMA device
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Store a PhysProxy port in Gicv3Redist
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Add named variable for GICD_TYPER.IDBits
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Read correct version of ICC_BPR register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Get a Gicv3Redistributor ptr from phys address
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Add several LPI methods in Gicv3Redistributor
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Take LPIs into account when interacting with...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Fix GICv3 LPIs priority value
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Disable LPI Configuration Table caching
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Check EnableLPIs before checking for pending...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: GICv3 LPI tables are using physical addresses
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Fix GICv3 LPI loop
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-05-02 Giacomo Travaglinidev-arm: Fix Bitwise operation in GICv3
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-29 Giacomo Travagliniarch-arm: Faults DebugFlag now printing inst opcode...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Move GICv3 (Re)Ditributor address in Realview.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Limit number of max PE in GICv3 to 128
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Add GICv4 extension switch in GICv3
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Check for maximum number of supported PE in...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-10 Giacomo Travaglinicpu: O3 switchFreeList checking VecElems instead of...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-28 Javier Setoainarch-arm: Fix use of bitwise operators on booleans
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-28 Giacomo Travagliniarch-arm: Fix index generation for VecElem operands
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Rename GIC maintenance interrupt from ppint...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Fix GICv3 overflow for INTID > 256
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-26 Giacomo Travaglinidev-arm: Set/Unset dma coherent mode from python
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-25 Javier Setoainarch-arm: Add missing fall-through defaults
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-22 Tiago Mucksim-se: Fixed initialization array size
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2019-03-22 Giacomo Travaglinibase: Fix CircularQueue's operator-= when negative...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-22 Giacomo Travaglinibase: Fix CircularQueue when diffing iterators
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-01 Giacomo Travaglinidev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-01 Giacomo Travaglinidev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-19 Giacomo Gabriellicpu: Add ISA* getter in Thread interface
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2019-02-18 Giacomo Travagliniarch-arm: Move GICv3 detection at startup time
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-18 Giacomo Travaglinibase: Fix enums checkpointing
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-15 Giacomo Travaglinicpu: Fix fast build broken due to unused variable
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-13 Giacomo Travagliniconfigs: simpoint-profile usable with NonCachingCPUs...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Ruben Ayrapetyanarch-arm: Fix initialization of PMU counters
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2019-02-07 Giacomo Travagliniconfigs, arch-arm: Using AddrRange for Realview mem_regions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-07 Giacomo Travagliniconfigs: Unifiy interpretation of Realview mem_regions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-01 Anouk Van Laerdev, arm: Removed contextId variable
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniconfigs: Enable DTB autogeneration in starter_fs.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autogeneration
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instruction
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2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Nicholas Lindsaypython: Always throw TypeError on slave-slave connections
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2019-01-24 Rekai Gonzalez-Alber... cpu-o3: O3 LSQ Generalisation
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2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Sascha Bischoffmem: Add tryTiming suppport to CommMonitor
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2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a VExpress_GEM5_V2 platform with GICv3...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a GICv3 model
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Jan-Peter Larssondev, arm: Warn on PL011 DMA disable
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added VGIC GICV_IIDR response
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Implement GIC-400 model from GicV2
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Move VGic from Realview.py to Gic.py
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added unimplemented GICv2 GICC_DIR
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-03 Curtis Dunhamarm: properly handle RES0/1 for SCTLRs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-08 Giacomo Travaglinibase, systemc: Fix clang compilation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-07 Giacomo Travaglinimem: Compile tracePacket only when TRACING_ON is defined
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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