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2019-07-19	Giacomo Travaglini	arch-arm: Implement ARMv8.1-HPD, Hierarchical permission... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-19	Giacomo Travaglini	arch-arm: Add HPD bit for TCR_EL2/EL3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-19	Giacomo Travaglini	arch-arm: Clean Fault generation when processing Long... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-19	Matteo Andreozzi	dev-arm: clang compatibility fix, added missing overrides Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-18	Gabor Dozsa	arch-arm: Add first-/non-faulting load instructions Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-18	Gabor Dozsa	sim: Add getter to fault virtual address Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-17	Giacomo Travaglini	arch-arm: Use ExceptionLevel type in TlbEntry Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-16	Giacomo Travaglini	dev-arm: Fix SMMUv3 ContextDescriptor pointer shift Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-07-16	Giacomo Travaglini	cpu: isDrained renamed to isCpuDrained Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-28	Michiel W. van Tol	base: Add argument to Coroutine class to not run on...	commit \| commitdiff \| tree
2019-06-26	Anouk Van Laer	arch, arm: Update miscRegs in getTE Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-26	Giacomo Travaglini	dev-arm: Remove un-needed Q_CONS_PROD_MASK macro Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-26	Adrian Herrera	dev-arm: drain implementation for SMMUv3 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-26	Adrian Herrera	dev-arm: pending SMMU transl update on constructor... Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-20	Giacomo Travaglini	configs: Fix NULL dram-lowp regressions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-17	Giacomo Travaglini	arch-arm: Move the memacc_code before op_wb in fp loads Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-17	Giacomo Travaglini	dev-arm: Reapply GICv3 changes that were lost during... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-09	Giacomo Travaglini	base: Provide a getter for Fiber::started boolean variable Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-09	Giacomo Travaglini	base: Rename TestFiber into SwitchingFiber Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-07	Giacomo Travaglini	arch-arm: Fix WalkerState,Descriptors default constructor Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-06-06	Stanislaw Czerniawski	dev-arm: Implement a SMMUv3 model - Giacomo Travaglini <giacomo.travaglini@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-24	Giacomo Travaglini	arch-arm: Fix fallthrough when trapping at EL2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-23	Giacomo Travaglini	arch-arm: Trap virtual accesses to GICv3 SGI registers Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-23	Giacomo Travaglini	arch-arm: Expose haveGicv3CPUInterface to the ISA interface Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-23	Giacomo Travaglini	arch-arm: Change mcrMrc15TrapToHyp signature Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-22	Giacomo Travaglini	dev-arm: Provide a GICv3 ITS Implementation Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-14	Giacomo Travaglini	Revert "cpu: fix how a thread starts up in MinorCPU" Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-14	Giacomo Travaglini	Revert "cpu: stop scheduling suspended threads in MinorCPU" Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-14	Giacomo Travaglini	Revert "cpu: fix branching when thread is suspended... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-03	Giacomo Travaglini	dev: StreamID generation in DMA device Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Store a PhysProxy port in Gicv3Redist Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Add named variable for GICD_TYPER.IDBits Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Read correct version of ICC_BPR register Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Get a Gicv3Redistributor ptr from phys address Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Add several LPI methods in Gicv3Redistributor Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Take LPIs into account when interacting with... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Fix GICv3 LPIs priority value Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Disable LPI Configuration Table caching Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Check EnableLPIs before checking for pending... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: GICv3 LPI tables are using physical addresses Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Fix GICv3 LPI loop Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-05-02	Giacomo Travaglini	dev-arm: Fix Bitwise operation in GICv3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-29	Giacomo Travaglini	arch-arm: Faults DebugFlag now printing inst opcode... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-29	Giacomo Travaglini	arch-arm: Report real instruction encoding when Undefined Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-26	Giacomo Travaglini	arch-arm: updateMiscReg not setting isHyp in aarch64 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	arch-arm: Remove un-needed hyp flag in TLBI operations Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	arch-arm: Correct target EL field in TLBI operations Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	dev-arm: Move GICv3 (Re)Ditributor address in Realview.py Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	dev-arm: Limit number of max PE in GICv3 to 128 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	dev-arm: Add GICv4 extension switch in GICv3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-25	Giacomo Travaglini	dev-arm: Check for maximum number of supported PE in... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-11	Giacomo Travaglini	arch-arm: Enable PMSELR_EL0 read in PMU Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-10	Giacomo Travaglini	cpu: O3 switchFreeList checking VecElems instead of... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-04-02	Giacomo Travaglini	dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-28	Javier Setoain	arch-arm: Fix use of bitwise operators on booleans Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-28	Giacomo Travaglini	arch-arm: Fix index generation for VecElem operands Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-27	Giacomo Travaglini	dev-arm: Rename GIC maintenance interrupt from ppint... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-27	Giacomo Travaglini	dev-arm: Fix GICv3 overflow for INTID > 256 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-27	Giacomo Travaglini	dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-26	Giacomo Travaglini	dev-arm: Set/Unset dma coherent mode from python Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-25	Javier Setoain	arch-arm: Add missing fall-through defaults Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-22	Tiago Muck	sim-se: Fixed initialization array size	commit \| commitdiff \| tree
2019-03-22	Giacomo Travaglini	base: Fix CircularQueue's operator-= when negative... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-22	Giacomo Travaglini	base: Fix CircularQueue when diffing iterators Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-01	Giacomo Travaglini	dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-03-01	Giacomo Travaglini	dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-19	Giacomo Gabrielli	cpu: Add ISA* getter in Thread interface	commit \| commitdiff \| tree
2019-02-18	Giacomo Travaglini	arch-arm: Move GICv3 detection at startup time Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-18	Giacomo Travaglini	base: Fix enums checkpointing Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-15	Giacomo Travaglini	cpu: Fix fast build broken due to unused variable Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-13	Giacomo Travaglini	configs: simpoint-profile usable with NonCachingCPUs... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-08	Giacomo Travaglini	arch-arm: Fix Virtual interrupts in AArch64 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-08	Giacomo Travaglini	arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-08	Giacomo Travaglini	arch-arm: Allow ArmPPI usage for PMU Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-08	Ruben Ayrapetyan	arch-arm: Fix initialization of PMU counters	commit \| commitdiff \| tree
2019-02-07	Giacomo Travaglini	configs, arch-arm: Using AddrRange for Realview mem_regions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-07	Giacomo Travaglini	configs: Unifiy interpretation of Realview mem_regions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-02-01	Anouk Van Laer	dev, arm: Removed contextId variable Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-30	Giacomo Travaglini	configs: Enable DTB autogeneration in starter_fs.py Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-30	Giacomo Travaglini	arch-arm, configs: Create single instance of DTB autogeneration Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch-arm: Remove floatReg operand type Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch-arm: Use VecElem instead of FloatReg for FP instruction	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch: Fix VecElem Operand generation in ISA parser Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	cpu, arch, arch-arm: Wire unused VecElem code in the... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	cpu: O3 rename using the flatIndex instead of index Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch-arm: Inital vector rename mode depending on A32/A64	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	cpu: Fix VecElemClass bugs in cpu models Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	cpu: Add VecElem entries in MinorCPU Scoreboard Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch-arm: Remove unused float operands Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Giacomo Travaglini	arch: Provide traceback when parsing ISA code Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-25	Nicholas Lindsay	python: Always throw TypeError on slave-slave connections	commit \| commitdiff \| tree
2019-01-24	Rekai Gonzalez-Alber...	cpu-o3: O3 LSQ Generalisation	commit \| commitdiff \| tree
2019-01-23	Giacomo Travaglini	arch-arm: Implement LoadAcquire/StoreRelease in AArch32 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-23	Giacomo Travaglini	arch-arm: IsStoreConditional flag set depending on... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-23	Giacomo Travaglini	arch-arm: Remove SWP and SWPB instructions Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-22	Giacomo Travaglini	arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-22	Sascha Bischoff	mem: Add tryTiming suppport to CommMonitor	commit \| commitdiff \| tree
2019-01-16	Giacomo Travaglini	arch-arm: Read VMPIDR instead of MPIDR when EL2 is... Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-16	Anouk Van Laer	arch-arm: Added TLBI_ALL EL2 instruction Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
2019-01-15	Giacomo Travaglini	cpu: Fix usage of setArchVecElem Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>	commit \| commitdiff \| tree
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