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Parameterize the issuer on the number of operands and results
2020-11-23
Cesar Strauss
Parameterize the issuer on the number of operands and...
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2020-11-22
Cesar Strauss
Refactor the ALU operation issuer into a class
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2020-11-22
Cesar Strauss
Port the ALU test case to the new parallel test style
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2020-11-22
Cesar Strauss
Add a GTKWave document to the ALU test case
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2020-11-19
Cesar Strauss
Separate input and output ports by color
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2020-11-19
Cesar Strauss
Explain the test cases
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2020-11-18
Cesar Strauss
Separate individual traces for each rel_o/go_i port
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2020-11-16
Cesar Strauss
Add a transaction counter to producers and consumers
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2020-11-15
Cesar Strauss
Implement ResultConsumer and port the Shifter unit...
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2020-11-14
Cesar Strauss
Move the DUT driver to within the test case process
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2020-11-14
Cesar Strauss
Fix and enable the regspec test for the Shifter
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2020-11-01
Cesar Strauss
Add a check for liveness.
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2020-10-31
Cesar Strauss
Check that the read and write counters differ at most...
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2020-10-31
Cesar Strauss
Remove stray comment
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2020-10-28
Cesar Strauss
Implement an operand producer that talks the rel_o...
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2020-10-24
Cesar Strauss
Create a GTKWave document for the test ALU unit tests
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2020-10-01
Cesar Strauss
Add GTKWave document to test_compunit_fsm
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2020-09-27
Cesar Strauss
Convert yet another few tests to be able to use latest...
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2020-09-26
Cesar Strauss
Convert a few more tests to be able to use cxxsim
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2020-09-24
Cesar Strauss
Use nmutil simulator module to simplify choosing among...
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2020-09-24
Cesar Strauss
Fix whitespace, remove unused imports
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2020-09-24
Cesar Strauss
Use nmutil simulator module to simplify choosing among...
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2020-09-22
Cesar Strauss
Port soc.experiment.alu_fsm to the new way of invoking...
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2020-09-20
Cesar Strauss
Add induction proof for the FSM Shifter
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2020-09-20
Cesar Strauss
Add bounded proof to FSM Shifter
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2020-09-20
Cesar Strauss
Let the formal engine create some test cases for the...
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2020-09-19
Cesar Strauss
Remove demonstration code
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2020-08-29
Cesar Strauss
Move new write_gtkw and its example to nmutil
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2020-08-23
Cesar Strauss
Allow an empty style, and passing default styles as...
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2020-08-23
Cesar Strauss
Add comment node type
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2020-08-23
Cesar Strauss
Add base and display styles
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2020-08-23
Cesar Strauss
Apply style from node own name
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2020-08-23
Cesar Strauss
Add color style
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2020-08-23
Cesar Strauss
Collect styles from the tuple
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2020-08-23
Cesar Strauss
Propagate the root style to all signals
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2020-08-22
Cesar Strauss
Move comments to the docstring
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2020-08-22
Cesar Strauss
Walk the DOM and emit the trace names
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2020-08-22
Cesar Strauss
First draft of a mini-language to describe GTKWave...
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2020-08-15
Cesar Strauss
Demonstrates string traces
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2020-08-15
Cesar Strauss
Demonstrates adding extra debug signals traces to the...
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2020-08-15
Cesar Strauss
Demonstrates creating stylish GTKWave "save" files...
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2020-07-20
Cesar Strauss
Document the move of sdir from data_i to op.
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2020-07-20
Cesar Strauss
Remove extra yield from test case.
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2020-07-19
Cesar Strauss
Implement control path and unit test.
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2020-07-18
Cesar Strauss
Implement the Shifter data path
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2020-07-18
Cesar Strauss
Document move of the next port data
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2020-07-09
Cesar Strauss
Define ports for a simple sequential Shifter
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2020-07-08
Cesar Strauss
Start the FSM-based ALU example.
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2020-07-07
Cesar Strauss
Clear input data along with valid_i
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2020-07-06
Cesar Strauss
Assert n.ready_i at the beginning of the cycle
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2020-07-06
Cesar Strauss
Remove wait state to demonstrate zero-delay reception.
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2020-07-06
Cesar Strauss
Simplify waiting loops
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2020-07-06
Cesar Strauss
Finally add some well needed comments
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2020-07-06
Cesar Strauss
Simplify waiting loops
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2020-07-06
Cesar Strauss
Add some wait states in each process
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2020-07-06
Cesar Strauss
Negate inputs after use
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2020-07-06
Cesar Strauss
Add other tests
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2020-07-06
Cesar Strauss
Implement receiver
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2020-07-06
Cesar Strauss
Implement sender.
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2020-07-06
Cesar Strauss
Begin a new parallel test
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2020-07-02
Cesar Strauss
Present the ALU result only when valid_o is active
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2020-06-28
Cesar Strauss
Start with a simpler test case
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2020-06-28
Cesar Strauss
Let p.ready_o be active while the test ALU is idle
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2020-06-28
Cesar Strauss
Add missing ports to the test ALU
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2020-06-13
Cesar Strauss
Wait for all active rel signals to be high, and only...
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2020-06-09
Cesar Strauss
Keep the sequencer in the "done" state until ready_i...
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2020-06-09
Cesar Strauss
Avoid a combinatorial loop on valid_o
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2020-06-07
Cesar Strauss
Assign the one-clock delay operation from ADD to SHR
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2020-06-07
Cesar Strauss
Try responding with ready_i on the same cycle as valid_o
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2020-06-07
Cesar Strauss
Assert valid_o one clock early, as alu_done is asserted
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2020-06-07
Cesar Strauss
Make the test ALU conform to the valid/ready protocol
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2020-06-03
Cesar Strauss
Check completion of the sub-processes
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2020-06-03
Cesar Strauss
Simplify immediate check
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2020-06-03
Cesar Strauss
Preliminary check of the alu protocol
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2020-06-03
Cesar Strauss
Pass along the operand, in the cycle in which go is...
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2020-06-02
Cesar Strauss
Allow at least one operand to be fetched
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2020-06-02
Cesar Strauss
Hold rdmaskn active during the busy_o cycle
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2020-06-01
Cesar Strauss
Add rdmaskn parameter and assert it along issue_i
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2020-05-29
Cesar Strauss
Allow immediate assertion of go in the same cycle as rel
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2020-05-29
Cesar Strauss
Correct typo
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2020-05-29
Cesar Strauss
Send a one-clock "go" pulse after a configurable number...
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2020-05-28
Cesar Strauss
Check that rd rises after issue_i, unless it's immediate
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2020-05-28
Cesar Strauss
Store and present parameters together with issue_i
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2020-05-27
Cesar Strauss
Move test case parameters to an "operation" member...
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2020-05-27
Cesar Strauss
Remove the monitor process
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2020-05-25
Cesar Strauss
Check that busy_o doesn't rise on its own
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2020-05-25
Cesar Strauss
Implement the issue_i/busy_o protocol check.
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2020-05-25
Cesar Strauss
Move process list to CompUnitParallelTest
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2020-05-25
Cesar Strauss
Fix detection of busy_o inside the monitor process
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2020-05-25
Cesar Strauss
Proof of concept of a parallel test
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2020-05-25
Cesar Strauss
Show oper_r and oper_i in the signal list, in simulation
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2020-05-24
Cesar Strauss
Avoid overwriting the first vcd file with the second one
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2020-05-24
Cesar Strauss
Rename the internal DFF of latchregisters to avoid...
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2020-05-23
Cesar Strauss
Add a few test cases with zero_a set, in combination...
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2020-05-23
Cesar Strauss
Allow zero_a to be set when simulating an operation
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2020-05-23
Cesar Strauss
Choose between RA (src1) and zero immediate, conditioned...
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2020-05-21
Cesar Strauss
Fixed typo and left-over from refactoring
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