| 2020-01-21 |
Giacomo Travaglini | tests: fs/linux/arm passing M5_PATH via commandline
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-17 |
Timothy Hayes | configs: MESI_Three_level python parameters
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commit | commitdiff | tree |
| 2020-01-17 |
Timothy Hayes | misc: add Arm build_opts for MESI_Three_Level and MOESI_hammer
|
commit | commitdiff | tree |
| 2020-01-15 |
Adrian Herrera | arch-arm: ELIsInHost, check VHE and SecEL2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-15 |
Adrian Herrera | arch-arm: Virtualization Host Extensions checking
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2020-01-14 |
Adrian Herrera | system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-10 |
Adrian Herrera | dev-arm: VExpress_GEM5_Base, fix daughterboard reference
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-09 |
Giacomo Travaglini | base, gpu-compute: Move gpu AMOs into the generic header
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-08 |
Giacomo Travaglini | arch, base: Move arm AtomicOpFunctor into the generic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-08 |
Giacomo Travaglini | base: Move AtomicOpFunctors to a dedicated header
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-07 |
Gabor Dozsa | cpu: Disable O3CPU value forwarding with write strobes
|
commit | commitdiff | tree |
| 2020-01-07 |
Gabor Dozsa | cpu: Use enums for O3CPU store value forwarding
|
commit | commitdiff | tree |
| 2020-01-07 |
Giacomo Travaglini | system-arm: GICv2/GICv3 have different Distributor...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-07 |
Giacomo Travaglini | system-arm: Rename ARM bootloader source
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2020-01-07 |
Giacomo Travaglini | system-arm: Rename ARM bootloader directories
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-07 |
Adrian Herrera | misc: Reflect changes of arm bootloader name
|
commit | commitdiff | tree |
| 2020-01-06 |
Adrian Herrera | arch-arm: Semihosting, specify files root dir
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-06 |
Michiel van Tol | dev-arm: Fix SMMUv3 walkMasks in page table ops
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-06 |
Giacomo Travaglini | dev-arm: Fix SMMUv3 16KB next-level table address masking
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-06 |
Adrian Herrera | dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-06 |
Adrian Herrera | configs-arm: enable PMU instantiation in CpuCluster
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2020-01-03 |
Giacomo Gabrielli | cpu: Fix issue with MinorCPU predicated-false mem....
|
commit | commitdiff | tree |
| 2020-01-03 |
Gabor Dozsa | cpu: Disable MinorCPU value forwarding with write strobes
|
commit | commitdiff | tree |
| 2019-12-23 |
Giacomo Travaglini | tests: Always print stderr in gem5 Fixtures
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-20 |
Giacomo Travaglini | configs: arm realview(64) regressions using VExpress_GEM5_V1
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-18 |
Adrian Herrera | arch-arm: Semihosting, fix SYS_FLEN
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-12-18 |
Adrian Herrera | sim: kernelExtras optional load addresses
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-12-18 |
Adrian Herrera | python: fix "fatal" usage in fdthelper
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-18 |
Adrian Herrera | arch-arm: Secure EL2 checking
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-18 |
Adrian Herrera | arch-arm: AArch64 trap check, arbitrary ECs/Imms
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-16 |
Adrian Herrera | sim: kernelExtras if no kernel provided
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-11 |
Giacomo Travaglini | arch-arm: Always initialize SVE memData
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-11 |
Giacomo Travaglini | arch-arm: Avoid creating an empty byteEnable vector
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-11 |
Giacomo Travaglini | cpu: Replace empty byteEnable check with Request::isMasked
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-11 |
Giacomo Travaglini | cpu: Fix coding style (byteEnable->byte_enable)
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-11 |
Giacomo Travaglini | cpu: Add byteEnable assertions to readMem and initateMemRead
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Adrian Herrera | dev-arm: GenericTimer, configurable base and low freqs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Adrian Herrera | dev-arm: GenericTimer, freq as 32-bit value
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Giacomo Travaglini | arch-arm: Disambuiguate NumFloatV7ArchRegs usage
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Giacomo Travaglini | arch-arm: Unify VLdmStm behaviour when reg out of index
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Giacomo Travaglini | arch-arm: Fix NumVecV7ArchRegs value (64->16)
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Giacomo Travaglini | arch-arm: Reorder arch/arm/registers.hh constants
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-10 |
Giacomo Travaglini | arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-09 |
Giacomo Travaglini | tests: AArch64 Linux as quick regressions (instead...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-09 |
Giacomo Travaglini | mem: Add Request::isMasked to check for byte strobing
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-12-09 |
Giacomo Travaglini | mem: Add byteEnable copy to Request copy constructor
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-12-03 |
Giacomo Travaglini | sim-se: Avoid function overloading for syscall implementation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-28 |
Adrian Herrera | dev-arm: device name in AmbaFake accesses
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | base, python: Allow dirname selection for the interpreter
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | configs: Add --redirects for syscall emulation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | base: Fix DPRINTF_UNCONDITIONAL on gem5.fast
|
commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | configs: Add root redirect path in SE mode only when set
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | sim-se: Check Path redirection when mmapping
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-27 |
Giacomo Travaglini | configs: Fix baremetal platform
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-11-26 |
Giacomo Travaglini | arch-arm: Make the Tarmac parsed registers case insensitive
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-11-25 |
Adrian Herrera | arch-arm: default MIDR for Armv8 ISA processors
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-25 |
Giacomo Travaglini | dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-21 |
Giacomo Travaglini | base: Remove tests making use of Big/LittleEndianOrder...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-18 |
Adrian Herrera | arch-arm: R/W interface to AArch32 HCR2 misc reg
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-18 |
Giacomo Travaglini | arch-arm: Fix short descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-18 |
Giacomo Travaglini | arch-arm: Fix long descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-14 |
Giacomo Travaglini | tests: Specify a non-default root folder for regressions
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-11-13 |
Adrian Herrera | arch-arm: fix routeToHyp for AArch64 in faults
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-12 |
Giacomo Travaglini | tests: Using super in arm_generic whenever possible
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-12 |
Giacomo Travaglini | tests: Using super for calling superclass __init__
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-12 |
Giacomo Travaglini | tests: Remove Noncoherent cache from regressions
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-11 |
Giacomo Travaglini | arch-arm: Fix TarmacParser handling of 64bit LD/ST
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-11 |
Giacomo Travaglini | arch-arm: Provide SVE support to the TarmacTracer
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-11 |
Giacomo Gabrielli | arch-arm: Provide SVE support to the TarmacParser
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-11-05 |
Giacomo Travaglini | arch-arm: Annotate original address in CMOs
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-05 |
Adrian Herrera | dev-arm: optional instantiation of GICv3 ITS
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-11-01 |
Adrian Herrera | arch-arm: generic method for getting an ArmSystem
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-11-01 |
Giacomo Travaglini | dev-arm: Add SMMUv3 to VExpress_GEM5_V*
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-31 |
Giacomo Travaglini | configs: Add baremetal.py example script
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-30 |
Giacomo Travaglini | base: Name segments after their index
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-22 |
Giacomo Travaglini | configs: Clean setupBootLoader signature
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-22 |
Giacomo Travaglini | configs: Do not assume bootmem is a System child
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-22 |
Giacomo Travaglini | dev-arm, configs: Using _on_chip_memory for on chip...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-16 |
Giacomo Travaglini | base: Using scoped string in DPRINTFNR
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-16 |
Giacomo Travaglini | base: Fix gem5.fast compilation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-15 |
Giacomo Travaglini | dev-arm: Carve out a portion of VExpress_GEM5 for the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-15 |
Giacomo Travaglini | configs: Add simpleSystem helper to generate devices...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-10 |
Giacomo Travaglini | arch-arm: Move generateDtb to ArmSystem
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-10 |
Giacomo Travaglini | dev-arm, configs: Remove RealViewPBX platform
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-03 |
Giacomo Travaglini | arch-arm: Annotate CM flag in AA64 CM Instructions
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-03 |
Giacomo Travaglini | arch-arm: Set CM bit in DataAbort
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-02 |
Giacomo Travaglini | sim: Mark System::getThreadContext method as const
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-02 |
Marc Mari Barcelo | dev-arm: Improve fault message on SMMUv3 translation...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-10-02 |
Marc Mari Barcelo | dev-arm: Fix address used to update the SMMUv3 Walk...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-02 |
Giacomo Travaglini | arch-arm: Create helper for sending events (SEV)
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | dev-arm: Conditionally enable HDLcd when doing DTB...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | dev-arm: Add HDLcd DTB autogeneration
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | arch-arm: PSTATE.PAN changes should inval cached regs...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-18 |
Adrian Herrera | system-arm: Add ITS node in platforms/vexpress_gem5_v2_base...
|
commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: Fix Data Abort ISS when caused by Atomic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: ISV bit in DataAbort should check for translation...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-16 |
Giacomo Travaglini | dev-arm: Allow IOMMU binding to HDLcd
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-13 |
Giacomo Travaglini | dev-arm: Store the IOMMU reference from within the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-13 |
Giacomo Travaglini | dev: Enable DTB IOMMU binding with a DMA object
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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