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Improve BTOR2 handling of undriven wires
2019-06-10
Udi Finkelstein
Fixed brojen $error()/$info/$warning() on non-generate...
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2019-05-03
Udi Finkelstein
Initial implementation of elaboration system tasks
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2018-10-24
Udi Finkelstein
Rename the generic "Syntax error" message from the...
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2018-09-24
Udi Finkelstein
Fixed issue #630 by fixing a minor typo in the previous...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-09-17
Udi Finkelstein
Fixed remaining cases where we check fo wire reg/wire...
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2018-08-23
Udi Finkelstein
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
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2018-08-20
Udi Finkelstein
Fixed all known specify/endspecify issues, without...
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2018-08-19
Udi Finkelstein
Yosys can now parse https://github.com/verilog-to-routing...
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2018-08-15
Udi Finkelstein
A few minor enhancements to specify block parsing.
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2018-06-06
Udi Finkelstein
Detect illegal port declaration, e.g input/output/inout...
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2018-06-05
Udi Finkelstein
Fixed typo (sikp -> skip)
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2018-06-05
Udi Finkelstein
Modified errors into warnings
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2018-06-05
Udi Finkelstein
reg_wire_error test needs the -sv flag so it is run...
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2018-03-27
Udi Finkelstein
First draft of Verilog parser support for specify blocks...
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2018-03-11
Udi Finkelstein
This PR should be the base for discussion, do not merge...
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2017-09-30
Udi Finkelstein
Turned a few member functions into const, esp. dumpAst...
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2017-09-30
Udi Finkelstein
Resolved classical Bison IF/THEN/ELSE shift/reduce...
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2017-09-26
Udi Finkelstein
$size() now works correctly for all cases!
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2017-09-26
Udi Finkelstein
$size() seems to work now with or without the optional...
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2017-09-26
Udi Finkelstein
enable $bits() and $size() functions only when the...
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2017-09-26
Udi Finkelstein
Added $bits() for memories as well.
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2017-09-26
Udi Finkelstein
$size() now works with memories as well!
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2017-09-26
Udi Finkelstein
Add $size() function. At the moment it works only on...
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