2019-02-07 | Austin Harris | arch-riscv: Enable support for riscv 32-bit in SE mode. Signed-off-by: Austin Harris <austinharris@utexas.edu> |
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2019-02-05 | Austin Harris | riscv: Get rid of ISA specific register types in Interrupts. Signed-off-by: Austin Harris <austinharris@utexas.edu> |
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2018-07-09 | Austin Harris | arch-riscv: Fix the srlw and srliw instructions. Signed-off-by: Austin Harris <austinharris@utexas.edu> |
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2017-12-12 | Austin Harris | config: Fix need to set ISA of switch cpus. Signed-off-by: Austin Harris <austinharris@utexas.edu> |
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2017-11-21 | Austin Harris | sim: Fix need to save address space info during serialization. Signed-off-by: Austin Harris <austinharris@utexas.edu> |
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