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Create a GTKWave document for the test ALU unit tests
2020-10-22
Luke Kenneth Casson...
add query about cross-domain on the JTAG enable of WB
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2020-10-22
Luke Kenneth Casson...
add detection and disable of Instruction Wishbone based...
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2020-10-22
Luke Kenneth Casson...
add detection and disable of LoadStore Wishbone based...
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2020-10-22
Luke Kenneth Casson...
add JTAG enable/disable of wishbone to TestIssuer
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2020-10-22
Luke Kenneth Casson...
add means to JTAG interface to enable/disable "stuff...
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2020-10-21
Luke Kenneth Casson...
fix up asserts (check correct pads/cores)
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2020-10-16
Luke Kenneth Casson...
experiment swapping dummy trap stage over to input
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2020-10-16
Luke Kenneth Casson...
re-enable tests
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2020-10-16
Luke Kenneth Casson...
manually run coresync clock for test issuer
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2020-10-16
Luke Kenneth Casson...
set defaults in pspec
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2020-10-16
Luke Kenneth Casson...
update submodule
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2020-10-16
Luke Kenneth Casson...
add extra (test dummy stage in trap to see if combinatorial...
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2020-10-16
Luke Kenneth Casson...
add LGPLv3+ notice and add copyright holders
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2020-10-15
Luke Kenneth Casson...
add commented-out connection to JTAG in ECP5 litex
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2020-10-15
Luke Kenneth Casson...
wrong pspec variable in selecting pll clock
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2020-10-15
Luke Kenneth Casson...
sorting out missing clock somewhere
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2020-10-15
Luke Kenneth Casson...
use "enable" and set default actions in getopt
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2020-10-15
Luke Kenneth Casson...
add extra variant to litex core
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2020-10-15
Luke Kenneth Casson...
syntax error
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2020-10-15
Luke Kenneth Casson...
disable gpio in litex core
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2020-10-15
Luke Kenneth Casson...
enable/disable litex irqs based on variant name
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2020-10-11
Luke Kenneth Casson...
add way to bypass PLL for ECP5 and sim
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2020-10-11
Luke Kenneth Casson...
comment out XICS/GPIO interrupt test, causes ECP5 litex...
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2020-10-11
Luke Kenneth Casson...
record commands for building ECP5
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2020-10-11
Luke Kenneth Casson...
litex sim.py operational
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2020-10-10
Luke Kenneth Casson...
add debug start/stop to firmware_upload script
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2020-10-10
Luke Kenneth Casson...
add DMI status / reset to firmware upload script
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2020-10-10
Luke Kenneth Casson...
add first version of firmware uploader
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2020-10-09
Luke Kenneth Casson...
use libresoc version of c4m-jtag repo
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2020-10-09
Luke Kenneth Casson...
submodule update
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2020-10-09
Luke Kenneth Casson...
drop in "undefined" function into ISAcaller namespace
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2020-10-09
Luke Kenneth Casson...
rename undef to undefined (preserving the fact that...
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2020-10-09
Luke Kenneth Casson...
missing yields in JTAG pads test to allow settling
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2020-10-08
Luke Kenneth Casson...
missing yields in JTAG pads test to allow settling
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2020-10-08
Luke Kenneth Casson...
minor icache cleanup
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2020-10-08
Luke Kenneth Casson...
add incoming PortInterface to be connected to LoadStoreCompUnit
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2020-10-08
Luke Kenneth Casson...
JTAG boundary scan test 1st attempt
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2020-10-08
Luke Kenneth Casson...
rework jtag test to use JTAG class not DMITAP
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2020-10-08
Luke Kenneth Casson...
split out jtag util functions to separate module
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2020-10-07
Luke Kenneth Casson...
missing invert_in field from shiftrot input record
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2020-10-07
Luke Kenneth Casson...
git submodule update
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2020-10-07
Luke Kenneth Casson...
reorder / reorganise reset signals slightly
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2020-10-06
Luke Kenneth Casson...
update comments on pimem.py
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2020-10-06
Luke Kenneth Casson...
comments
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2020-10-06
Luke Kenneth Casson...
add ports function to DummyPLL
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2020-10-06
Luke Kenneth Casson...
use pdecode2.do not pdecode2.e in test_pipe_caller...
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2020-10-06
Luke Kenneth Casson...
skip Decode2ToOperand from PowerDecodeSubset
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2020-10-06
Luke Kenneth Casson...
comment SRR1 mem.exception
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2020-10-06
Luke Kenneth Casson...
add SRR1 setting for LDST memory exception trap
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2020-10-06
Luke Kenneth Casson...
passing LDSTException over to Trap Pipeline
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2020-10-06
Luke Kenneth Casson...
add LDSTException decode/handling in PowerDecoder2
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2020-10-06
Luke Kenneth Casson...
make LDSTException fields added from list of fieldnames
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2020-10-06
Luke Kenneth Casson...
move LDSTException to mem_types
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2020-10-06
Luke Kenneth Casson...
submodule update
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2020-10-06
Luke Kenneth Casson...
add LDSTException to PortInterface
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2020-10-06
Luke Kenneth Casson...
add sdr bypass routing via JTAG boundary scan
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2020-10-05
Luke Kenneth Casson...
add debug / investigation print statements
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2020-10-05
Luke Kenneth Casson...
whoops fix syntax error
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2020-10-05
Luke Kenneth Casson...
whoops fix syntax error
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2020-10-05
Luke Kenneth Casson...
return test rather than "if test return True else False"
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2020-10-05
Luke Kenneth Casson...
whitespace
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2020-10-05
Luke Kenneth Casson...
whitespace
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2020-10-04
Luke Kenneth Casson...
significant reorg of the litex pinspecs to use pinmux...
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2020-10-04
Luke Kenneth Casson...
submodule update
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2020-10-04
Luke Kenneth Casson...
remove ls180io import
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2020-10-04
Luke Kenneth Casson...
move ls180io.py back into ls180.py
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2020-10-03
Luke Kenneth Casson...
allow i2c to be routed via JTAG
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2020-10-03
Luke Kenneth Casson...
nope. put it back and connect to platform pads in...
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2020-10-03
Luke Kenneth Casson...
move iopad litex creation to ls180soc.py
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2020-10-03
Luke Kenneth Casson...
minor reorg on JTAG, allow alternative pinset dict...
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2020-10-02
Luke Kenneth Casson...
add pinmux generator to create litex pinmap
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2020-10-02
Luke Kenneth Casson...
add pinmux as submodule
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2020-10-01
Luke Kenneth Casson...
arg CacheRam read output needs delay by 1 cycle
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2020-10-01
Luke Kenneth Casson...
do not pass cache row array around, just the current row
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2020-10-01
Luke Kenneth Casson...
revert bug in icache wishbone ack
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2020-10-01
Luke Kenneth Casson...
add clksel, pll to ls180
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2020-10-01
Luke Kenneth Casson...
create dummy PLL block, connect up to core and clock...
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2020-09-30
Luke Kenneth Casson...
add I2C into ls180
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2020-09-30
Luke Kenneth Casson...
add ASIC version of I2C Master
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2020-09-30
Luke Kenneth Casson...
clean up row store and wb adr in icache
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2020-09-30
Luke Kenneth Casson...
hmm only set wishbone address if ack is actually received
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2020-09-30
Luke Kenneth Casson...
add more debug prints in icache
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2020-09-30
Luke Kenneth Casson...
remove more reviewed comments
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2020-09-30
Luke Kenneth Casson...
remove reviewed comments
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2020-09-30
Luke Kenneth Casson...
comb on wr_index not sync
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2020-09-30
Luke Kenneth Casson...
start removing reviewed comments
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2020-09-30
Luke Kenneth Casson...
use same constant name (confusing otherwise)
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2020-09-30
Luke Kenneth Casson...
need asserts
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2020-09-30
Luke Kenneth Casson...
halve the number of icache lines for now
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2020-09-30
Luke Kenneth Casson...
use Repl rather than for-loop to copy bit
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2020-09-30
Luke Kenneth Casson...
move loop invariant test out of loop
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2020-09-30
Luke Kenneth Casson...
reduce size of ilang file by a factor of FIVE
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2020-09-30
Luke Kenneth Casson...
store tag in temp signal
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2020-09-30
Luke Kenneth Casson...
reduce gate usage by getting cache row only not entire...
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2020-09-30
Luke Kenneth Casson...
fix read_tag to use word_select correctly
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2020-09-30
Luke Kenneth Casson...
forgot to add PLRUs as submodules
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2020-09-28
Luke Kenneth Casson...
reduce not-connected IO pins
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2020-09-28
Luke Kenneth Casson...
missing pspec
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2020-09-28
Luke Kenneth Casson...
connect SDRAM dqm to wrdata_mask
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2020-09-28
Luke Kenneth Casson...
lots of sorting out iopads
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