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Temporarily derive blackbox modules in hierarchy to evaluate port widths
2018-01-04
Clifford Wolf
Temporarily derive blackbox modules in hierarchy to...
Signed-off-by:
Clifford Wolf
<clifford@clifford.at>
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2017-12-24
Clifford Wolf
Add "no driver for signal bit" error msg to btor back-end
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2017-12-24
Clifford Wolf
Bugfix in verilog_defaults argument parser
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2017-12-19
Clifford Wolf
Fix minor typo in "prep" help message
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2017-12-17
Clifford Wolf
Simple fix BTOR memory encoding
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2017-12-17
Clifford Wolf
Improve BTOR memory encoding
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2017-12-15
Clifford Wolf
Merge branch 'btor-ng'
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2017-12-15
Clifford Wolf
Add array support to btor back-end
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2017-12-14
Clifford Wolf
Add $anyconst/$anyseq support to btor back-end
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Add yosys-smtbmc VCD writer support for memories with...
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2017-12-14
Clifford Wolf
Fix a bug in clk2fflogic memory handling
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Add clk2fflogic memory support
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2017-12-14
Clifford Wolf
Add smt2 back-end support for async write memories
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2017-12-14
Clifford Wolf
Add RTLIL::Const::is_fully_ones()
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2017-12-14
Clifford Wolf
Add SigSpec::is_fully_ones()
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2017-12-13
Clifford Wolf
Check for memories in clk2fflogic
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2017-12-12
Clifford Wolf
Add "write_btor -s" mode
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2017-12-12
Clifford Wolf
Add state initval handling to btor back-end
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2017-12-12
Clifford Wolf
Add btor back-end support for 'x' constants
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2017-12-12
Clifford Wolf
Add SigSpec::is_fully_ones()
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2017-12-12
Clifford Wolf
Add warnings for driver-driver conflicts between FFs...
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2017-12-11
Clifford Wolf
Add btor $shift/$shiftx support
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2017-12-10
Clifford Wolf
Fix btor back-end shift handling
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2017-12-10
Clifford Wolf
Add support for $pmux in btor back-end
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2017-12-10
Clifford Wolf
Add support for more cell types to btor back-end
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2017-12-10
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-10
Clifford Wolf
Add support for Verific PRIM_SVA_NOT properties
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2017-12-09
Clifford Wolf
Add Verific OPER_SVA_STABLE support
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2017-12-09
Clifford Wolf
Refactoring Verific SVA rewriter
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2017-12-09
Clifford Wolf
Fix btor concat
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2017-12-09
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-03
Clifford Wolf
Use "hg ... --insecure" for cloning/pulling ABC
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2017-12-02
Clifford Wolf
Update ABC to hg rev 31fc97b0aeed
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2017-12-02
Clifford Wolf
Fix error handling for nested always/initial
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2017-12-01
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-27
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-27
Clifford Wolf
Fixed "yosys-smtbmc -g" handling of no solution
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2017-11-27
Clifford Wolf
Fixed "yosys-smtbmc -g" handling of no solution
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2017-11-24
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-24
Clifford Wolf
Bugfixes in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Progress in new BTOR back-end
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2017-11-23
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-23
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-11-23
Clifford Wolf
Add Verilog "automatic" keyword (ignored in synthesis)
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2017-11-23
Clifford Wolf
Progress with new BTOR backend
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2017-11-23
Clifford Wolf
Add skeleton for new BTOR back-end
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2017-11-23
Clifford Wolf
Remove old BTOR back-end
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2017-11-18
Clifford Wolf
Accept real-valued delay values
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2017-11-16
Clifford Wolf
Add "synth_ice40 -vpr"
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2017-11-08
Clifford Wolf
Add support for editline as replacement for readline
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2017-10-31
Clifford Wolf
Add "ltp" command
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2017-10-29
Clifford Wolf
Fix SMT2 handling of initstate in sub-modules
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2017-10-26
Clifford Wolf
Fix memory corruption bug in opt_rmdff
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2017-10-26
Clifford Wolf
Fix typo in opt_clean log message
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2017-10-25
Clifford Wolf
Improve smtio performance by using reader thread, not...
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2017-10-25
Clifford Wolf
Use separate writer thread for talking to SMT solver...
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2017-10-25
Clifford Wolf
Improve p_* functions in smtio.py
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2017-10-25
Clifford Wolf
Disable OSX in .travis.yml
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2017-10-25
Clifford Wolf
Add ENABLE_DEBUG config flag
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2017-10-25
Clifford Wolf
Update ABC to hg rev f6838749f234
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2017-10-25
Clifford Wolf
Remove vhdl2verilog
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2017-10-25
Clifford Wolf
Capsulate smt-solver read/write in separate functions
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2017-10-25
Clifford Wolf
Fix a bug in yosys-smtbmc in ROM handling
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2017-10-20
Clifford Wolf
Remove PSL example from tests/sva/
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2017-10-20
Clifford Wolf
Remove all PSL support code from verific.cc
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2017-10-14
Clifford Wolf
Revert 90be0d8 as it causes endless loops for some...
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2017-10-13
Clifford Wolf
Add "verific -vlog-libdir"
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2017-10-13
Clifford Wolf
Add "verific -vlog-incdir" and "verific -vlog-define"
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2017-10-13
Clifford Wolf
Update Verific README
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2017-10-12
Clifford Wolf
Add Verific fairness/liveness support
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2017-10-11
Clifford Wolf
Update ABC to hg rev 6283c5d99b06
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2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-10-10
Clifford Wolf
Start work on pre-processor for Verific SVA properties
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2017-10-10
Clifford Wolf
Rewrite ABC output to include proper net names in timing...
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2017-10-10
Clifford Wolf
Add timing constraints to osu035 example
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2017-10-10
Clifford Wolf
Remove some dead code
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2017-10-10
Clifford Wolf
Allow $past, $stable, $rose, $fell in $global_clock...
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2017-10-07
Clifford Wolf
Add $shiftx support to verilog front-end
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2017-10-06
Clifford Wolf
Update ABC to hg rev 0fc1803a77c0
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2017-10-05
Larry Doolittle
Clean whitespace and permissions in techlibs/intel
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2017-10-05
Clifford Wolf
Improve handling of Verific errors
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2017-10-04
Clifford Wolf
Improve Verific error handling, check VHDL static asserts
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2017-10-04
Clifford Wolf
Add blackbox command
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2017-10-04
Clifford Wolf
Fix nasty bug in Verific bindings
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2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
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2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
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2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
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2017-10-03
Clifford Wolf
Rename "write_verilog -nobasenradix" to "write_verilog...
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2017-09-29
Clifford Wolf
Add first draft of eASIC back-end
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2017-09-29
Clifford Wolf
Fix synth_ice40 doc regarding -top default
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2017-09-29
Clifford Wolf
Allow $size and $bits in verilog mode, actually check...
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2017-09-27
Clifford Wolf
Increase maximum LUT size in blifparse to 12 bits
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2017-09-26
Clifford Wolf
Parse reals as string in JSON front-end
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2017-09-26
Clifford Wolf
Merge branch 'vlogpp-inc-fixes'
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2017-09-26
Clifford Wolf
Minor coding style fix
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2017-09-26
Clifford Wolf
Merge branch 'master' of https://github.com/combinatorylogic...
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