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arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare
2021-01-25 Giacomo Travagliniarch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2021-01-23 Giacomo Travagliniarch-arm: Fix Compare and Swap Pair instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2021-01-19 Giacomo Travaglinitests: Fix syntax error in cpu_tests/test.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2021-01-18 Giacomo Travagliniarch-arm: dtb_addr is already encoding the loadAddrOffset
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2021-01-07 Giacomo Travagliniconfigs: Remove default bootscript option for fs_bigLITTLE.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-12-08 Giacomo Travaglinicpu: MinorCPU not updating cycle counter value
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-12-03 Giacomo Travaglinicpu, sim: Remove unused System::totalNumInst
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-27 Giacomo Travagliniutil: Port util to python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-25 Giacomo Travagliniarch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-25 Giacomo Travagliniarch-arm: Add SECURE_RD/WR flags to miscRegInfo
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-25 Giacomo Travaglinidev: -Wdeprecated-copy not available on all supported...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-20 Giacomo Travaglinipython: Remove SortedDict from python utilities
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-20 Giacomo Travagliniscons, python: Remove SmartDict from python utilities
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-20 Giacomo Travaglinipython: Fix toBool converter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-19 Giacomo Travaglinifastmodel: Replace xrange with range to be python3...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-19 Giacomo Travaglinifastmodel: Use BaseMMU in the CortexR52 wrapper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-09 Giacomo Travaglinitests: Add realview64-kvm.py test to quick regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-09 Giacomo Travaglinitests: Add realview64-kvm.py testing platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-09 Giacomo Travaglinitests: Update guest binaries used by regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-03 Giacomo Travagliniarch-arm: Do not use _flushMva for TLBI IPA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-03 Giacomo Travagliniarch-arm: TlbEntry flush to be considered as functional...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-03 Giacomo Travagliniarch-arm: Fix implementation of TLBI_VMALL instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-03 Giacomo Travagliniarch-arm: Add el2Enabled cached variable
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-03 Giacomo Travaglinicpu, fastmodel: Remove the old getDTBPtr/getITBPtr...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinidev-arm: Instantiate SCMI in VExpress_GEM5 platforms
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinidev-arm: SCMI Implementation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinidev-arm: Implement Arm MHU (Message Handling Unit)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinitests: System is expecting a kvm_vm param for KvmVM
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinikvm, arm: Add parameter to force simulation of Gicv2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinidev-arm: Add doorbell interface class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-11-02 Giacomo Travaglinidev-arm: Define a ParentMem object for DTB autogen
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-27 Giacomo Travaglinisim: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-27 Giacomo Travagliniarch-x86: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-27 Giacomo Travagliniarch-sparc: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-27 Giacomo Travagliniarch-riscv: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-26 Giacomo Travaglinimem: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-23 Giacomo Travagliniarch-arm: Fix implementation of TLBI ALLEx instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-23 Giacomo Travagliniarch-arm: Rewrite the TLB flushing interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-23 Giacomo Travagliniarch-arm: Reimplement TLB::flushAll
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-23 Giacomo Travagliniarch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-21 Giacomo Travagliniarch: Use getTlb in BaseMMU to reduce boilerplate
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-21 Giacomo Travagliniarch-arm: Replace any getDTBPtr/getITBPtr usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-21 Giacomo Travaglinicpu: Remove unused demapInstPage and demapDataPage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-21 Giacomo Travaglinimisc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-20 Giacomo Travaglinidev-arm: Adding a SRAM in VExpress_GEM5_V1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travagliniarch-arm: Implement ArmPMU DTB generation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travaglinidev: Use generateFdtProperty in the PioDevice
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travaglinidev-arm: Use generateFdtProperty in the GenericTimer
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travaglinidev-arm: Automate FdtProperty generation with ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travaglinidev-arm, fastmodel: Rewrite Gic.interruptCells
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-17 Giacomo Travaglinidev-arm: Define ArmInterruptType
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-15 Giacomo Travagliniconfigs: Remove dangling reference to bus port in devices.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-08 Giacomo Travagliniarch-arm: Default ArmSystem to AArch64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-07 Giacomo Travaglinifastmodel: Add IrisMMU model
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-10-07 Giacomo Travagliniarch: Add generic BaseMMU
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-30 Giacomo Travaglinicpu: Never use a empty byteEnable
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-30 Giacomo Travagliniarch-x86: Add byteEnable mask in x86 memhelpers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-30 Giacomo Travagliniarch-arm: Using new "raw" memhelpers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-30 Giacomo Travagliniarch: Add raw read/writeMem helpers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-30 Giacomo Travagliniarch: Do value-initialization for MemOperand
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-29 Giacomo Travagliniext: Add timing indications to every TestCase
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-22 Giacomo Travaglinidev-arm: Implement GICv4.1 GICD_TYPER2 as RES0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-22 Giacomo Travagliniarch-arm: TLBI ALLE2IS should broadcast to the IS domain
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-13 Giacomo Travagliniarch-arm: Fix ArmISA namespace requirement for Arm KVM
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-09-09 Giacomo Travagliniarch-arm: Fix ArmISA namespace requirement for TME...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Fix coding style in addressTranslation methods
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Check if PAC is implemented before executing...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-28 Giacomo Travagliniarch-arm: Introduce HavePACExt helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Rewrite addressTranslation to use BitUnions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Remove deadcode from AArch64 address translation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-26 Giacomo Travagliniarch-arm: Refactor Address Translation (AT) code
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Early checking if debug is enabled in TLB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Rename SelfDebug member variables
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-18 Giacomo Travagliniarch-arm: Remove setters from SoftwareStep
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Add Xen compilation to gen_arm_fs_files.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Remove dependency check
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Allow the short -j option in gen_arm_fs_files.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-15 Giacomo Travagliniutil: Change gen_arm_fs_files.py to allow selective...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Use isSecure variable for Stage2Lookup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix physmem NS attribute in VMSAv8-32 descriptors
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: VSTTBR_EL2 doesn't contain a VMID field
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Disable HVC when SCR_EL3.HCE is 0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix XN in TLB permissions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-14 Giacomo Travagliniarch-arm: Fix SoftwareStep::debugExceptionReturnSS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-10 Giacomo Travagliniarch-arm: Reduce boilerplate when extracting SelfDebug...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-08-10 Giacomo Travaglinidev-arm: Fix <timer>_CTL_EL<x>.ISTATUS when masking...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Avoid code duplication in Pl111
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Relax size constraint on AMBA ID registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Fix DTB autogen for HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make the Sp805 use the new ArmInterruptPin...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Sp804 use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Pl011 UART use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Introduce the active boolean for ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive PPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive SPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Gicv3 maintenance interrupt never cleared
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Check for security attribute when writing...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Remove SPI/PPI range check in Gicv3 class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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