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json: Add help message for `signed` field
2021-10-26
Rupert Swarbrick
Split out logic for reprocessing an AstModule
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2021-08-13
Rupert Swarbrick
Generate an RTLIL representation of bind constructs
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2021-07-20
Rupert Swarbrick
Use new read_id_num helper function elsewhere in hierarchy.cc
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2021-07-20
Rupert Swarbrick
Extract connection checking logic from expand_module...
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2021-07-16
Rupert Swarbrick
Add support for parsing the SystemVerilog 'bind' construct
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2021-07-15
Rupert Swarbrick
Add a test for interfaces on modules loaded on-demand
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2021-07-15
Rupert Swarbrick
Extract missing module support in hierarchy.cc to a...
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2021-07-14
Rupert Swarbrick
Delete unused found_init variable
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2021-06-17
Rupert Swarbrick
Move interface expansion in hierarchy.cc into a helper...
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2021-06-14
Rupert Swarbrick
Simplify some RTLIL destructors
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2021-05-14
Rupert Swarbrick
Change the type of current_module to Module
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2021-05-14
Rupert Swarbrick
Use range-based for loop in AST::process
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2020-07-03
Rupert Swarbrick
Add newlines to help text for dfflegalize
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2020-05-28
Rupert Swarbrick
Fix small typos in documentation for hierarchy command
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2020-05-27
Rupert Swarbrick
Pass some more args by reference in select.cc
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2020-05-27
Rupert Swarbrick
Minor optimisations in select.cc's match_ids function
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2020-05-27
Rupert Swarbrick
Silence warning in select.cc
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2020-05-26
Rupert Swarbrick
Silence spurious warning in Verilog lexer when compiling...
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2020-05-26
Rupert Swarbrick
Simplify a modport check in hierarchy.cc
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2020-05-26
Rupert Swarbrick
Minor optimisation in Module::wire() and Module::cell()
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2020-05-26
Rupert Swarbrick
Use default copy constructor for RTLIL::SigBit
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2020-05-26
Rupert Swarbrick
Use c_str(), not str() for IdString/std::string ==...
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2020-03-27
Rupert Swarbrick
Add support for SystemVerilog-style `define to Verilog...
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