git.libre-soc.org Git - nmigen.git/search

2020-06-05	Shawn Anastasio	hdl.rec: preserve shapes when constructing a layout.	commit \| commitdiff \| tree
2020-05-08	Gwenhael Goavec...	vendor.lattice_machxo2: generate binary bitstreams.	commit \| commitdiff \| tree
2020-04-24	awygle	lib.fifo: add r_rst output for AsyncFIFO{,Buffered}.	commit \| commitdiff \| tree
2020-04-24	awygle	hdl.ir: typecheck `convert(ports=)` more carefully.	commit \| commitdiff \| tree
2020-04-23	Teguh Hofstee	back.verilog: add workaround for evaluation Verific...	commit \| commitdiff \| tree
2020-04-22	Teguh Hofstee	back.verilog: make Yosys version check compatible with...	commit \| commitdiff \| tree
2020-04-16	anuejn	hdl.rec: make Record inherit from UserValue.	commit \| commitdiff \| tree
2020-04-13	Dan Ravensloft	hdl.ast: add Value.{rotate_left,rotate_right}.	commit \| commitdiff \| tree
2020-03-20	WRansohoff	vendor.lattice_ice40: add support for SB_[LH]FOSC as...	commit \| commitdiff \| tree
2020-03-15	Stuart Olsen	back.pysim: implement modulus operator.	commit \| commitdiff \| tree
2020-03-14	awygle	Correctly handle resets in AsyncFIFO.	commit \| commitdiff \| tree
2020-03-08	awygle	lib.cdc: extract AsyncFFSynchronizer.	commit \| commitdiff \| tree
2020-02-16	awygle	nmigen.compat.genlib.cdc: add PulseSynchronizer.	commit \| commitdiff \| tree
2020-02-16	awygle	nmigen.lib.cdc: port PulseSynchronizer.	commit \| commitdiff \| tree
2020-01-27	whitequark	Update README.	commit \| commitdiff \| tree