2020-08-27 |
Luke Kenneth Casson... | https://bugs.libre-soc.org/show_bug.cgi?id=476
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2020-08-27 |
Luke Kenneth Casson... | xer so is not being passed through to CR0
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2020-08-27 |
Luke Kenneth Casson... | really bad hack to fix simulator bug in carry handling
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2020-08-27 |
Luke Kenneth Casson... | augment addme test case to show bug #476
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2020-08-27 |
Luke Kenneth Casson... | add addze and addme uni tests
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2020-08-27 |
Luke Kenneth Casson... | incompatibility with POWER9 on mulhw/u due to lack...
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2020-08-27 |
Luke Kenneth Casson... | overflow-enable does not occur on shift operations
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2020-08-27 |
Luke Kenneth Casson... | oink, write_cr shiftrot record width was zero (??)
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2020-08-27 |
Luke Kenneth Casson... | sorting out shift_rot to use new output stage data...
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2020-08-27 |
Luke Kenneth Casson... | need to read SO if Rc=1
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2020-08-27 |
Luke Kenneth Casson... | reorg of SO handling related to CR0
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2020-08-26 |
Luke Kenneth Casson... | use sub-test in logical test_pipe_caller
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2020-08-26 |
Luke Kenneth Casson... | investigating div fsm and simulator bug
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2020-08-25 |
Luke Kenneth Casson... | although shift-rot does not alter XER.so it still needs...
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2020-08-25 |
Luke Kenneth Casson... | add way to capture CR from DMI in litex sim
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2020-08-25 |
Luke Kenneth Casson... | add CR read to DMI interface
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2020-08-25 |
Luke Kenneth Casson... | shorten using temp vars
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2020-08-25 |
Luke Kenneth Casson... | add CR DMI interface
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2020-08-25 |
Luke Kenneth Casson... | add crxor unit test to qemu
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2020-08-24 |
Luke Kenneth Casson... | argh, reading regfile over DMI was overlapped and corrupting...
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2020-08-24 |
Luke Kenneth Casson... | add isel CR tests to run on qemu (confirmed working)
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2020-08-24 |
Luke Kenneth Casson... | make it easier to select FSM/Pipe DIV unit
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2020-08-24 |
Luke Kenneth Casson... | fix *another* ld-update-related timing / FSM issue
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2020-08-24 |
Luke Kenneth Casson... | tidyup / shuffle after review
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2020-08-24 |
Luke Kenneth Casson... | remove default parameter
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2020-08-24 |
Luke Kenneth Casson... | "WAY" does not exist - range(NUM_WAYS) was intended
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2020-08-24 |
Luke Kenneth Casson... | use WAY_BITS in appropriate locations
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2020-08-24 |
Luke Kenneth Casson... | reminder that the license (reflecting what is in setup...
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2020-08-23 |
Luke Kenneth Casson... | update copyright notices to include additional primary...
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2020-08-23 |
Luke Kenneth Casson... | add load algebraic immediate unit test
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2020-08-23 |
Luke Kenneth Casson... | add algebraic ld tests lwax, lwaux
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2020-08-23 |
Luke Kenneth Casson... | bring "core stopped" signal out through DMI interface
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2020-08-23 |
Luke Kenneth Casson... | add in DMI "stat" loop which monitors core "stopping"
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2020-08-23 |
Luke Kenneth Casson... | comment why litex sim mem map is altered
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2020-08-23 |
Luke Kenneth Casson... | multiply does not have invert_in, zero_a or invert_out
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2020-08-22 |
Luke Kenneth Casson... | rename invert_a to invert_in because logical inverts RB
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2020-08-22 |
Luke Kenneth Casson... | update submodule
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2020-08-22 |
Luke Kenneth Casson... | load bios not 1.bin unit test
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2020-08-22 |
Luke Kenneth Casson... | add extra div regression tests
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2020-08-22 |
Luke Kenneth Casson... | add eqv to logical unit test
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2020-08-22 |
Luke Kenneth Casson... | add nor and nand to unit test
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2020-08-22 |
Luke Kenneth Casson... | moved to div pipe temporarily in compunits
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2020-08-22 |
Luke Kenneth Casson... | bug in andc and orc, complement was taking place on...
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2020-08-22 |
Luke Kenneth Casson... | extend addis test
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2020-08-22 |
Luke Kenneth Casson... | add andc and orc tests, failing because RB needs inversion...
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2020-08-22 |
Luke Kenneth Casson... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi...
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2020-08-22 |
Luke Kenneth Casson... | submodule update
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2020-08-22 |
Luke Kenneth Casson... | add regression test for nonzero addis
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2020-08-22 |
Luke Kenneth Casson... | add means to run microwatt test binaries
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2020-08-22 |
Luke Kenneth Casson... | r0 zero tests on addis, fails
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2020-08-22 |
Luke Kenneth Casson... | investigating litex sdrinit function
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2020-08-22 |
Luke Kenneth Casson... | add pseudo-op conversion
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2020-08-22 |
Luke Kenneth Casson... | add start of litex bios counter loop
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2020-08-21 |
Luke Kenneth Casson... | remove extraneous comments
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2020-08-21 |
Luke Kenneth Casson... | testing 64-bit wishbone bus after 32-bit *still* fails...
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2020-08-21 |
Luke Kenneth Casson... | get litex sim enabled with 32-bit wishbone bus
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2020-08-21 |
Luke Kenneth Casson... | ld/st bus reduction test operational
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2020-08-21 |
Luke Kenneth Casson... | first test of down-converted load/store from 64 to...
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2020-08-21 |
Luke Kenneth Casson... | first test of down-converted load/store from 64 to...
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2020-08-21 |
Luke Kenneth Casson... | add in WishboneDownConvert into LoadStoreUnitInterface
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2020-08-21 |
Luke Kenneth Casson... | comment formatting
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2020-08-21 |
Luke Kenneth Casson... | remove default values
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2020-08-21 |
Luke Kenneth Casson... | just range(the_constant)
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2020-08-20 |
Luke Kenneth Casson... | bugfix wishbone downconvert using wb sram 64-to-32...
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2020-08-20 |
Luke Kenneth Casson... | add a wishbone upconverter
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2020-08-19 |
Luke Kenneth Casson... | rename and document fields in shift_rot proof
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2020-08-19 |
Luke Kenneth Casson... | comments in dcache
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2020-08-19 |
Luke Kenneth Casson... | more subtle interactions between wishbone bus when...
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2020-08-19 |
Luke Kenneth Casson... | bit of a reorg of mul proof, tracking down missing
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2020-08-19 |
Luke Kenneth Casson... | move long mul tests to separate unit test
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2020-08-19 |
Luke Kenneth Casson... | use "Mask" class which is more gate-efficient than...
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2020-08-19 |
Luke Kenneth Casson... | set up StageChain of 3 mul stages
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2020-08-18 |
Luke Kenneth Casson... | fix spr state test
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2020-08-18 |
Luke Kenneth Casson... | add comment in dcache.py
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2020-08-17 |
Luke Kenneth Casson... | move Mask to nmutil
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2020-08-17 |
Luke Kenneth Casson... | turn SelectableInt less/greater into signed versions.
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2020-08-17 |
Luke Kenneth Casson... | use longer memtest in litex sim
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2020-08-17 |
Luke Kenneth Casson... | adjust litex bios cmp test
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2020-08-17 |
Luke Kenneth Casson... | fix signed variants of cmp in alu
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2020-08-17 |
Luke Kenneth Casson... | add new cmp test for alu
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2020-08-17 |
Luke Kenneth Casson... | use shift module in mmu. to be moved to nmutil
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2020-08-16 |
Luke Kenneth Casson... | attempting to track down bug in litex bios memtest
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2020-08-16 |
Luke Kenneth Casson... | read delay on getting regfile data
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2020-08-16 |
Luke Kenneth Casson... | limit debug reporting in litex sim to range of pc
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2020-08-16 |
Luke Kenneth Casson... | cmp test from litex bios
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2020-08-16 |
Luke Kenneth Casson... | remove vhdl comments
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2020-08-16 |
Luke Kenneth Casson... | use simple one-line mask-generation
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2020-08-16 |
Luke Kenneth Casson... | fix LD/ST pimem issue with rising_edge detection
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2020-08-16 |
Luke Kenneth Casson... | missing vars, spelling corrections
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2020-08-16 |
Luke Kenneth Casson... | big reorg, shuffle code to functions, makes the FSM...
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2020-08-16 |
Luke Kenneth Casson... | spelling error, move perm_ok to local
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2020-08-16 |
Luke Kenneth Casson... | more comment removal
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2020-08-16 |
Luke Kenneth Casson... | more remove comments
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2020-08-16 |
Luke Kenneth Casson... | removing more comments, tidyup
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2020-08-16 |
Luke Kenneth Casson... | restore incorrect removal of zero-Cat at LHS (should...
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2020-08-16 |
Luke Kenneth Casson... | continue tidyup, comment removal/review. use byte_reverse...
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2020-08-16 |
Luke Kenneth Casson... | fix batch of syntax errors found by running mmu.py
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2020-08-16 |
Luke Kenneth Casson... | begin tidyup, removing comments after line-by-line...
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2020-08-15 |
Luke Kenneth Casson... | thanks to daveshah, added simulation of dram
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2020-08-15 |
Luke Kenneth Casson... | rather big change to interaction between regfile and...
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