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machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO...
2021-02-23 William D. Jonesmachxo2: Use attrmvcp pass to move LOC and src attributes...
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2021-02-23 William D. Jonesmachxo2: Add missing OSCH oscillator primitive.
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2021-02-23 William D. Jonesmachxo2: Add believed-to-be-correct tribuf test.
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2021-02-23 William D. Jonesmachxo2: Add passing fsm, mux, and shifter tests.
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2021-02-23 William D. Jonesmachxo2: Add add_sub test. Fix tests to include FACADE_IO...
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2021-02-23 William D. Jonesmachxo2: Add -noiopad option to synth_machxo2.
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2021-02-23 William D. Jonesmachxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
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2021-02-23 William D. Jonesmachxo2: Fix cells_sim typo where OFX1 was multiply...
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2021-02-23 William D. Jonesmachxo2: synth_machxo2 now maps ports to FACADE_IO.
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2021-02-23 William D. Jonesmachxo2: Add initial value for Q in FACADE_FF.
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2021-02-23 William D. Jonesmachxo2: Add FACADE_IO simulation model. More comments...
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2021-02-23 William D. Jonesmachxo2: Add FACADE_SLICE simulation model.
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2021-02-23 William D. Jonesmachxo2: Improve FACADE_FF simulation model.
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2021-02-23 William D. Jonesmachxo2: Improve LUT4 techmap. Use same output port...
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2021-02-23 William D. Jonesmachxo2: Add dffe test.
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2021-02-23 William D. Jonesmachxo2: Add dff.ys test, fix another cells_map.v typo.
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2021-02-23 William D. Jonesmachxo2: Fix more oversights in machxo2 models. logic...
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2021-02-23 William D. Jonesmachxo2: Add test/arch/machxo2 directory (test does...
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2021-02-23 William D. Jonesmachxo2: Fix typos. test/arch/run-test.sh passes.
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2021-02-23 William D. Jonesmachxo2: Create basic techlibs and synth_machxo2 pass.
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2021-02-22 Karol Gugalafrontend: json: parse negative values
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2021-02-22 Marcelina Kościelnickaassertpmux: Fix crash on unused $pmux output.
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2021-01-29 Marcelina Kościelnickaast: fix dump_vlog display of casex/casez
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2021-01-26 Marcelina Kościelnickaxilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-26 Marcelina Kościelnickaxilinx: Add FDRSE_1, FDCPE_1.
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2021-01-14 Marcelina Kościelnickaopt_share: Fix X and CO signal width for shifted $alu...
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2020-12-21 Marcelina Kościelnickaxilinx: Add some missing blackbox cells.
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2020-12-21 Marcelina Kościelnickaxilinx: Regenerate cells_xtra.v using Vivado 2020.2
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2020-12-17 Marcelina Kościelnickaxilinx: Add FDDRCPE and FDDRRSE blackbox cells.
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2020-12-14 Marcelina Kościelnickatiminginfo: Error instead of segfault on const signals.
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2020-10-24 Marcelina Kościelnickaxilinx: Fix attributes_test.ys
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2020-10-22 Marcelina Kościelnickamemory_dff: Fix needlessly duplicating enable bits.
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2020-10-21 Marcelina Kościelnickabtor: Use Mem helper.
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2020-10-21 Marcelina Kościelnickasmt2: Use Mem helper.
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2020-10-21 Marcelina Kościelnickaverilog_backend: Use Mem helper.
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2020-10-21 Marcelina Kościelnickasim: Use Mem helper.
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2020-10-21 Marcelina Kościelnickaclk2fflogic: Use Mem helper.
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2020-10-21 Marcelina Kościelnickaopt_mem: Use Mem helpers.
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2020-10-21 Marcelina Kościelnickamemory_bram: Use Mem helpers.
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2020-10-21 Marcelina Kościelnickamemory_map: Use Mem helpers.
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2020-10-21 Marcelina Kościelnickamemory_unpack: Use Mem helpers.
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2020-10-21 Marcelina Kościelnickamemory_collect: Use Mem helpers.
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2020-10-21 Marcelina Kościelnickamemory_nordff: Use Mem helpers.
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2020-10-21 Marcelina KościelnickaAdd new helper structures to represent memories.
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2020-10-08 Marcelina Kościelnickaopt_clean: Better memory handling.
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2020-08-28 Dan Ravensloftintel_alm: better map wide but shallow multiplies
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2020-08-27 Marcelina Kościelnickadfflegalize: Fix decision tree for adffe.
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2020-08-26 Dan Ravensloftintel_alm: Add multiply signedness to cells
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2020-08-20 Marcelina Kościelnickasynth_intel: Remove incomplete Arria 10 GX support.
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2020-08-20 Dan Ravensloftintel: move Cyclone V support to intel_alm
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2020-08-20 Marcelina Kościelnickatechmap/shift_shiftx: Remove the "shiftx2mux" special...
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2020-08-18 XiretzaEnsure \A_SIGNED is never used with $shiftx
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2020-08-18 XiretzaRespect \A_SIGNED for $shift
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2020-08-17 Marcelina Kościelnickaopt_share: Refactor, fix some bugs.
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2020-08-13 Dan Ravensloftintel_alm: fix typo in MISTRAL_MUL27X27 cell name
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2020-08-12 Dan Ravensloftintel_alm: add more megafunctions. NFC.
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2020-08-09 Marcelina Kościelnickaopt_clean: Fix module keep rules.
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2020-08-07 Marcelina KościelnickaRemove now-redundant dff2dffe pass.
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2020-08-07 Marcelina KościelnickaRemove now-redundant dff2dffs pass.
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2020-08-07 Marcelina Kościelnickapeepopt: Remove now-redundant dffmux pattern.
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2020-08-07 Marcelina KościelnickaRemove now-redundant opt_rmdff pass.
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2020-08-07 Marcelina KościelnickaReplace opt_rmdff with opt_dff.
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2020-08-05 Marcelina Kościelnickapeeopt.shiftmul: Add a signedness check.
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2020-08-05 Marcelina Kościelnickatechmap.CONSTMAP: Handle outputs before inputs.
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2020-08-04 Marcelina Kościelnickapeepopt.muldiv: Add a signedness check.
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2020-08-02 Marcelina Kościelnickatechmap: Add support for [] wildcards in techmap_celltype.
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2020-07-30 Marcelina KościelnickaAdd dffunmap pass.
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2020-07-30 Marcelina Kościelnickaopt_expr: Remove -clkinv option, make it the default.
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2020-07-30 Marcelina Kościelnickasynth_ice40: Use opt_dff.
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2020-07-30 Marcelina Kościelnickasynth_xilinx: Use opt_dff.
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2020-07-30 Marcelina Kościelnickaasync2sync: Support all FF types.
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2020-07-30 Marcelina KościelnickaAdd opt_dff pass.
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2020-07-30 Marcelina Kościelnickaverilog_backend: Add handling for all FF types.
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2020-07-29 Marcelina Kościelnickaopt_expr: Fix handling of $_XNOR_ cells with A = B.
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2020-07-28 Marcelina Kościelnickaffinit: Fortify the code a bit.
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2020-07-27 Marcelina Kościelnickaequiv_induct: Fix up assumption for $equiv cells in...
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2020-07-27 Dan Ravensloftintel_alm: direct M10K instantiation
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2020-07-26 Dan Ravensloftintel_alm: increase abc9 -W
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2020-07-24 Marcelina Kościelnickaasync2sync: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickamemory_dff: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickaproc_dlatch: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickapmux2shift: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickawreduce: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickatechmap: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickashregmap: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickaabc: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickadffinit: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickazinit: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickadfflegalize: Refactor to use FfInitVals.
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2020-07-24 Marcelina Kościelnickaclk2fflogic: Support all FF types.
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2020-07-24 Marcelina Kościelnickasatgen: Add support for dffe, sdff, sdffe, sdffce cells.
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2020-07-23 Marcelina KościelnickaAdd utility module for representing flip-flops.
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2020-07-23 Marcelina Kościelnickamemory_dff: recognize more dff cells
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2020-07-23 Marcelina KościelnickaAdd utility module for dealing with init attributes.
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2020-07-22 Keith RothmanRemove EXPLICIT_CARRY logic.
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2020-07-21 Marcelina Kościelnickatechmap: Add _TECHMAP_CELLNAME_ special parameter.
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2020-07-20 Marcelina Kościelnickacelltypes: Fix EN port name for some FF types.
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2020-07-18 Marcelina Kościelnickasatgen: Move importCell out of the header.
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2020-07-17 Marcelina Kościelnickasf2: Emit CLKINT even if -clkbuf not passed
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2020-07-17 Marcelina Kościelnickaanlogic: Fix FF mapping.
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