| 2020-02-08 |
whitequark | README: consolidate requirements in the Installation...
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commit | commitdiff | tree |
| 2020-02-07 |
whitequark | test_build_res: fix after commit 3e2ecdf2.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | build.res,vendor: place clock constraint on port, not...
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | xilinx_{7series,ultrascale}: run `report_methodology`.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | test_lib_fifo: define all referenced FSM states.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.dsl: make referencing undefined FSM states an error.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.ir: type check ports.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | back.pysim: emit toplevel inputs in VCD files as well.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | back.pysim: make `write_vcd(traces=)` actually use...
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.dsl: reject name mismatch in `m.domains.<name>...
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.dsl: type check when adding to m.domains.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support.
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commit | commitdiff | tree |
| 2020-02-06 |
whitequark | hdl.mem: document Memory.
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commit | commitdiff | tree |
| 2020-02-04 |
whitequark | hdl.{ast,dsl}: allow whitespace in bit patterns.
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | hdl.ast: update documentation for Signal.
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value.
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | build.plat: align pipeline with Fragment.prepare().
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | hdl.dsl: don't allow inheriting from Module.
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | hdl.ast: warn on unused property statements (Assert...
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commit | commitdiff | tree |
| 2020-02-01 |
whitequark | _unused: extract must-use logic from hdl.ir.
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commit | commitdiff | tree |
| 2020-01-31 |
whitequark | hdl.dsl: add missing case width check for Enum values.
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commit | commitdiff | tree |
| 2020-01-31 |
whitequark | README: clarify relationship to Migen.
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commit | commitdiff | tree |
| 2020-01-31 |
whitequark | hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error.
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commit | commitdiff | tree |
| 2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals.
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commit | commitdiff | tree |
| 2020-01-27 |
whitequark | Update README.
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commit | commitdiff | tree |
| 2020-01-18 |
whitequark | hdl.ir: resolve hierarchy conflicts before creating...
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commit | commitdiff | tree |
| 2020-01-17 |
whitequark | hdl.xfrm: transform drivers as well in DomainRenamer.
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commit | commitdiff | tree |
| 2020-01-12 |
whitequark | Remove everything deprecated in nmigen 0.1.
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commit | commitdiff | tree |
| 2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements...
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commit | commitdiff | tree |
| 2019-12-15 |
whitequark | hdl.mem: fix src_loc_at in ReadPort, WritePort.
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commit | commitdiff | tree |
| 2019-12-02 |
whitequark | back.pysim: fix miscompilation of Signal(unsigned)...
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commit | commitdiff | tree |
| 2019-12-02 |
whitequark | hdl.ast: actually remove simulator commands.
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commit | commitdiff | tree |
| 2019-11-28 |
whitequark | back.pysim: redesign the simulator.
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commit | commitdiff | tree |
| 2019-11-27 |
whitequark | back.rtlil: infer bit width for instance parameters.
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commit | commitdiff | tree |
| 2019-11-26 |
whitequark | hdl.ir: for instance ports, prioritize defs over uses.
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commit | commitdiff | tree |
| 2019-11-18 |
whitequark | back.rtlil: extend shorter operand of a binop when...
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commit | commitdiff | tree |
| 2019-11-15 |
whitequark | build.plat: in Platform.add_file(), allow adding exact...
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commit | commitdiff | tree |
| 2019-11-15 |
whitequark | test: add tests for build.plat.Platform.add_file.
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commit | commitdiff | tree |
| 2019-11-09 |
whitequark | hdl.rec: fix Record.like() being called through a subclass.
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commit | commitdiff | tree |
| 2019-11-07 |
whitequark | hdl.ir: lower domains before resolving hierarchy conflicts.
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commit | commitdiff | tree |
| 2019-11-02 |
whitequark | Improve .gitignore.
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commit | commitdiff | tree |
| 2019-10-28 |
whitequark | back.verilog: remove $verilog_initial_trigger after...
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commit | commitdiff | tree |
| 2019-10-26 |
whitequark | test: use `#nmigen:` magic comment instead of monkey...
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commit | commitdiff | tree |
| 2019-10-26 |
whitequark | hdl.ir: allow disabling UnusedElaboratable warning...
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commit | commitdiff | tree |
| 2019-10-26 |
whitequark | back.rtlil: avoid exponential behavior when legalizing...
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commit | commitdiff | tree |
| 2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account...
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commit | commitdiff | tree |
| 2019-10-26 |
whitequark | hdl.ast: simplify {bit,word}_select with constant offset.
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commit | commitdiff | tree |
| 2019-10-21 |
whitequark | Explicitly restrict prelude imports.
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commit | commitdiff | tree |
| 2019-10-17 |
whitequark | compat.fhdl.specials: fix argument parsing compatibility.
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commit | commitdiff | tree |
| 2019-10-16 |
whitequark | lib.io: use keyword-only arguments in Pin().
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commit | commitdiff | tree |
| 2019-10-16 |
whitequark | setup: fix commit 5198d99b.
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commit | commitdiff | tree |
| 2019-10-16 |
whitequark | back.verilog: fix Yosys version check.
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commit | commitdiff | tree |
| 2019-10-15 |
whitequark | setup: don't append local version for tags.
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commit | commitdiff | tree |
| 2019-10-14 |
whitequark | vendor.lattice_ice40: fix commit 88649def.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | vendor.lattice_{ice40,ecp5}: fix typo.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | vendor.lattice_ice40: use pcf files instead of pre...
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | build.plat: batch files use EQU, not EQ.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | {,_}tools→{,_}utils
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | vendor.lattice_{ice40,ecp5}: emit Verilog as well,...
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | build.plat: fold emit_prelude() into emit_commands().
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | hdl.ir: allow ClockSignal and ResetSignal in ports.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | hdl.ir: cast instance port connections to Values.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | compat.fhdl.decorators: improve backwards compatibility.
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commit | commitdiff | tree |
| 2019-10-13 |
whitequark | compat.fhdl.bitcontainer: update Value.wrap call.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | doc: bring COMPAT_SUMMARY up to date.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | compat.genlib.fsm: add migration warning.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | compat.fhdl.decorators: add migration warnings.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | compat.fhdl.structure: remove SPECIAL_* constants.
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commit | commitdiff | tree |
| 2019-10-12 |
whitequark | _tools: extract most utility methods to a private package.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | Rename remaining `wrap` methods to `cast`.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor...
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: deprecate Signal.{range,enum}.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: add an explicit Shape class, included in prelude.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator}
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: simplify enum handling.
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commit | commitdiff | tree |
| 2019-10-11 |
whitequark | hdl.ast: Value.{wrap→cast}
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | vendor.xilinx_ultrascale: new supported family.
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | xilinx_7series: add grade platform property.
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | vendor.lattice_machxo2: new supported family.
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | vendor: yosys is a required tool for all Verilog-based...
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | README: add device support matrix.
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commit | commitdiff | tree |
| 2019-10-10 |
whitequark | vendor.intel: add Quartus support.
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commit | commitdiff | tree |
| 2019-10-09 |
whitequark | examples: update blinky, add some explanatory text...
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commit | commitdiff | tree |
| 2019-10-09 |
whitequark | build.plat: elaborate result of create_missing_domain...
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commit | commitdiff | tree |
| 2019-10-09 |
whitequark | build.plat: don't create default sync domain as reset...
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commit | commitdiff | tree |
| 2019-10-09 |
whitequark | build.plat,vendor: always synchronize reset in default...
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commit | commitdiff | tree |
| 2019-10-06 |
whitequark | back.rtlil: don't crash legalizing values with no branches.
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commit | commitdiff | tree |
| 2019-10-04 |
whitequark | back.rtlil: avoid unsoundness for division by zero.
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commit | commitdiff | tree |
| 2019-10-04 |
whitequark | hdl.ast: prohibit signed divisors.
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commit | commitdiff | tree |
| 2019-10-03 |
whitequark | build.dsl: accept Pins(invert=True).
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commit | commitdiff | tree |
| 2019-10-02 |
whitequark | hdl.ast: don't crash on Mux(<bool>, ...).
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commit | commitdiff | tree |
| 2019-10-02 |
whitequark | back.rtlil: don't cache wires for legalized switch...
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commit | commitdiff | tree |
| 2019-10-02 |
whitequark | back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow...
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commit | commitdiff | tree |
| 2019-10-02 |
whitequark | back.rtlil: it is not necessary to match binop operand...
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commit | commitdiff | tree |
| 2019-09-30 |
whitequark | rpc: add support for Yosys RPC protocol.
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commit | commitdiff | tree |
| 2019-09-28 |
whitequark | hdl.ast: actually implement the // operator.
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commit | commitdiff | tree |
| 2019-09-28 |
whitequark | hdl.dsl: add a diagnostic for `m.d.submodules += ...`.
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commit | commitdiff | tree |
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