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simple_ram: Add pipelining support
2019-10-30 Benjamin Herrenschmidtsimple_ram: Add pipelining support
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-30 Benjamin Herrenschmidtintercon: Generate stall signals for non-pipelined...
...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-30 Benjamin Herrenschmidtwb_arbiter: Forward stall signals
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-30 Benjamin Herrenschmidticache_tb: Initialize stop_mark
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-30 Benjamin Herrenschmidtwishbone: Add stall signal
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-30 Benjamin Herrenschmidtpp_uart: reformat
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin HerrenschmidtReduce wishbone address size to 32-bit
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin HerrenschmidtMake it possible to change wishbone address size
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtdcache: Add testbench
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtinsn: Simplistic implementation of icbi
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtinsn: Implement isync instruction
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidticache & dcache: Fix store way variable
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtdcache: Cleanup (mostly cosmetic)
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidticache/dcache: Make both caches 32 lines, 2 ways
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtdcache: Introduce an extra cycle latency to make timing
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtdcache: Add a dcache
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidticache: Reduce simulation warnings
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtcache_ram: Add write-enables
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-23 Benjamin Herrenschmidtplru: Improve sensitivity list
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-18 Benjamin Herrenschmidticache_tb: Improve test and include test file
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-16 Benjamin Herrenschmidtcommon: Reformat
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-16 Benjamin Herrenschmidtexecute1: Remove mux on "write_data" and "rc" outputs
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-16 Benjamin Herrenschmidtcrhelpers: Constraint "crnum" integer
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-16 Benjamin Herrenschmidtexecute1: Reformat
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-16 Benjamin Herrenschmidtwriteback: Remove a mux leg on data_in
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidticache: Set associative icache
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidtplru: Add a simple PLRU module
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidtfetch2: Remove blank line
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidticache: Use narrower block RAMs
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidtfetch/icache: Fit icache in BRAM
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidtfetch1: Simplify a bit
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-08 Benjamin Herrenschmidticache: Reformat icache
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-03 Benjamin Herrenschmidtregister_file: Move GPRs into distributed RAM
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-01 Benjamin Herrenschmidtdebug/sim: Make connect/disconnect messages quieter
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-01 Benjamin HerrenschmidtAdd MCRF instruction
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-10-01 Benjamin HerrenschmidtImplement absolute branches
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtImprove PLL/MMCM clocks configuration
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtDon't reset JTAG request register asynchronously
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtMultiply needs to be 16 stages to fix all timing issues
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin Herrenschmidtcorefile: Remove duplicate wishbone_debug_master
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin Herrenschmidtfpga: Arty A7's don't need multiple filesets
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin Herrenschmidtexecute1: simplify flush_out
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtReformat fetch2
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtMove fetch2 <-> icache definitions
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtRemove unused pipe_stop in Fetch1ToFetch2Type
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtFix PLL reset signal name in toplevel
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtSimplify fetch1
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtReformat fetch1
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-30 Benjamin HerrenschmidtUpdate dependency
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtAdd distclean to Makefile
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtNew C based JTAG debug tool
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtAdd core debug module
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org
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2019-09-20 Benjamin HerrenschmidtAdd jtag support in simulation via a socket
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtAdd DMI address decoder
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtWishbone debug module
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtAdd a debug (DMI) bus and a JTAG interface to it on...
...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-20 Benjamin HerrenschmidtUse a 3 way WB arbiter and cleanup fpga toplevel
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtSwitch soc to use std_ulogic
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtPass wishbone record to bram memory module
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtRework wishbone slave address decoding
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtMove wishbone arbiter out of the core
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtRe-indent and reformat soc.vhdl
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-10 Benjamin HerrenschmidtSplit FPGA toplevel from soc
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-09 Benjamin Herrenschmidtdecode1 array fix header
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-09 Benjamin HerrenschmidtUse simulated UART in core test bench
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-09 Benjamin HerrenschmidtMake sim poll non-blocking
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2019-09-09 Benjamin HerrenschmidtAdd simulated UART design
 ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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