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stats: Update t1000 stats to match recent changes
2012-10-23
Andreas Hansson
stats: Update t1000 stats to match recent changes
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2012-10-15
Andreas Hansson
Mem: Fix incorrect logic in bus blocksize check
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2012-10-15
Andreas Hansson
Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15
Andreas Hansson
Mem: Separate the host and guest views of memory backing...
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2012-10-15
Andreas Hansson
Checkpoint: Make system serialize call children
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2012-10-15
Andreas Hansson
Mem: Use deque instead of list for bus retries
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2012-10-15
Andreas Hansson
Fix: Address a few minor issues identified by cppcheck
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2012-10-15
Andreas Hansson
Stats: Update stats for cache timings in cycles
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2012-10-15
Andreas Hansson
Mem: Use cycles to express cache-related latencies
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2012-10-15
Andreas Hansson
Stats: Update memtest stats after setting clock
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2012-10-15
Andreas Hansson
Configs: Set the memtest clock to a reasonable value
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2012-10-15
Andreas Hansson
Stats: Update stats for new default L1-to-L2 bus clock...
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2012-10-15
Andreas Hansson
Regression: Use CPU clock and 32-byte width for L1...
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2012-10-15
Andreas Hansson
Stats: Update stats for use of two-level builder
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2012-10-15
Andreas Hansson
Regression: Use addTwoLevelCacheHierarchy in configs
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2012-10-15
Andreas Hansson
Clock: Inherit the clock from parent by default
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2012-10-15
Andreas Hansson
Param: Fix proxy traversal to support chained proxies
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2012-10-15
Andreas Hansson
Mem: Use range operations in bus in preparation for...
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2012-10-11
Andreas Hansson
Mem: Determine bus block size during initialisation
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2012-10-11
Andreas Hansson
Doxygen: Update the version of the Doxyfile
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2012-09-27
Andreas Hansson
Configs: Fix memtest cache latency to match new parameters
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2012-09-27
Andreas Hansson
Configs: Fix memtest.py by moving the system port
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2012-09-24
Andreas Hansson
Stats: Update stats for twosys-tsunami after setting...
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2012-09-24
Andreas Hansson
Regression: Set the clock for twosys-tsunami CPUs
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2012-09-21
Andreas Hansson
SimpleDRAM: A basic SimpleDRAM regression
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2012-09-21
Andreas Hansson
DRAM: Introduce SimpleDRAM to capture a high-level...
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator regression
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator
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2012-09-21
Andreas Hansson
Mem: Tidy up bus member variables types
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2012-09-21
Andreas Hansson
Scons: Verbose messages when dependencies are not installed
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2012-09-19
Andreas Hansson
Mem: Remove the file parameter from AbstractMemory
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2012-09-19
Andreas Hansson
AddrRange: Transition from Range<T> to AddrRange
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2012-09-19
Andreas Hansson
AddrRange: Simplify Range by removing stream input...
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2012-09-19
Andreas Hansson
AddrRange: Remove unused range_multimap
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2012-09-19
Andreas Hansson
AddrRange: Simplify AddrRange params Python hierarchy
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2012-09-18
Andreas Hansson
Stats: Update stats to reflect SimpleMemory bandwidth
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2012-09-18
Andreas Hansson
Mem: Add a maximum bandwidth to SimpleMemory
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2012-09-14
Andreas Hansson
gcc: Enable Link-Time Optimization for gcc >= 4.6
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2012-09-14
Andreas Hansson
scons: Add a target for google-perftools profiling
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2012-09-14
Andreas Hansson
scons: Restructure ccflags and ldflags
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2012-09-14
Andreas Hansson
scons: Use c++0x with gcc >= 4.4 instead of 4.6
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2012-09-13
Andreas Hansson
Stats: Remove the reference stats that are no longer...
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2012-09-11
Andreas Hansson
clang: Fix issues identified by the clang static analyzer
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2012-09-11
Andreas Hansson
Checkpoint: Pass maxtick to avoid undefined variable
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2012-09-10
Andreas Hansson
Ruby: Bump the stats after recent memory controller...
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2012-09-10
Andreas Hansson
AddrRange: Remove the unused range_ops header
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2012-09-10
Andreas Hansson
Inet: Remove the SackRange and its use
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2012-09-10
Andreas Hansson
Device: Update stats for PIO and PCI latency change
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2012-09-10
Andreas Hansson
Device: Bump PIO and PCI latencies to more reasonable...
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2012-09-07
Andreas Hansson
Param: Transition to Cycles for relevant parameters
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2012-08-28
Andreas Hansson
Clock: Add a Cycles wrapper class and use where applicable
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2012-08-28
Andreas Hansson
Clock: Rework clocks to avoid tick-to-cycle transformations
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2012-08-28
Andreas Hansson
Port: Stricter port bind/unbind semantics
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2012-08-28
Andreas Hansson
Checker: Bump the realview-o3-checker regression
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2012-08-28
Andreas Hansson
Checker: Fix checker CPU ports
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2012-08-28
Andreas Hansson
swig: Disable unused value warning with llvm 3.1 compilers
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2012-08-22
Andreas Hansson
DMA: Refactor the DMA device and align timing and atomic
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2012-08-22
Andreas Hansson
Packet: Remove NACKs from packet and its use in endpoints
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2012-08-22
Andreas Hansson
Bridge: Remove NACKs in the bridge and unify with packet...
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2012-08-22
Andreas Hansson
Port: Extend the QueuedPort interface and use where...
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2012-08-21
Andreas Hansson
Device: Remove overloaded pio_latency parameter
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2012-08-21
Andreas Hansson
CPU: Remove overloaded function_trace_start parameter
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2012-08-21
Andreas Hansson
PacketQueue: Allow queuing in the same tick as desired...
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2012-08-21
Andreas Hansson
EventManager: Remove test for NULL pointer in constructor
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2012-08-21
Andreas Hansson
Clock: Make Tick unsigned and remove UTick
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2012-08-21
Andreas Hansson
Clock: Move the clock and related functions to ClockedObject
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2012-08-21
Andreas Hansson
Checkpoint: Fix broken checkpointing functionality
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2012-07-23
Andreas Hansson
Config: Use clock option in se/fs script and pass to...
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2012-07-23
Andreas Hansson
Bridge: Use EventWrapper instead of Event subclass...
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2012-07-21
Andreas Hansson
Regression: Fix topologies path in failing pc-simple...
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2012-07-12
Andreas Hansson
Mem: Make SimpleMemory single ported
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2012-07-12
Andreas Hansson
scons: Add LIBRARY_PATH from the user environment to...
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2012-07-09
Andreas Hansson
EventManager: Rename queue accessor and remove cast...
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2012-07-09
Andreas Hansson
Mem: Make members relating to range and size constant
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2012-07-09
Andreas Hansson
Port: Hide the queue implementation in SimpleTimingPort
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2012-07-09
Andreas Hansson
Stats: Updates due to bus changes
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2012-07-09
Andreas Hansson
Port: Align port names in C++ and Python
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2012-07-09
Andreas Hansson
Bus: Make the default bus width 8 bytes instead of 64
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2012-07-09
Andreas Hansson
Bus: Split the bus into separate request/response layers
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2012-07-09
Andreas Hansson
Bus: Add a notion of layers to the buses
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2012-07-09
Andreas Hansson
Bus: Replace tickNextIdle and inRetry with a state...
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2012-07-09
Andreas Hansson
Port: Make getAddrRanges const
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2012-07-09
Andreas Hansson
Port: Add getAddrRanges to master port (asking slave...
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2012-07-09
Andreas Hansson
Port: Add isSnooping to slave port (asking master port)
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2012-07-09
Andreas Hansson
Port: Move retry from port base class to Master/SlavePort
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2012-07-09
Andreas Hansson
Fix: Address a few benign memory leaks
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2012-07-02
Andreas Hansson
gcc: Fix warnings for gcc 4.7 and clang 3.1
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2012-06-20
Andreas Hansson
swig: Use SWIG from environment when determining version
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2012-06-18
Andreas Hansson
Build: Point to the appropriate tcmalloc package
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2012-06-08
Andreas Hansson
Timing CPU: Remove a redundant port pointer
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2012-06-08
Andreas Hansson
Power: Fix MaxMiscDestRegs which was set to zero
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2012-05-31
Andreas Hansson
Bus: Split the bus into a non-coherent and coherent bus
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2012-05-09
Andreas Hansson
Stats: Fix stats to match output after changeset 8800b05e1cb3
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2012-05-30
Andreas Hansson
gcc: Small fixes to compile with gcc 4.7
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2012-05-30
Andreas Hansson
Bus: Remove redundant packet parameter from isOccupied
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2012-05-30
Andreas Hansson
Bus: Turn the PortId into a transport function parameter
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2012-05-30
Andreas Hansson
Packet: Unify the use of PortID in packet and port
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2012-05-30
Andreas Hansson
Packet: Updated comments for src and dest fields
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2012-05-30
Andreas Hansson
Bridge: Split deferred request, response and sender...
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2012-05-24
Andreas Hansson
Cache: Remove dangling doWriteback declaration
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