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Merge pull request #2006 from jersey99/signed-in-rtlil-wire
2020-05-28
Rupert Swarbrick
Fix small typos in documentation for hierarchy command
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2020-05-26
Rupert Swarbrick
Silence spurious warning in Verilog lexer when compiling...
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2020-05-26
Rupert Swarbrick
Minor optimisation in Module::wire() and Module::cell()
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2020-05-26
Rupert Swarbrick
Use default copy constructor for RTLIL::SigBit
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2020-05-26
Rupert Swarbrick
Use c_str(), not str() for IdString/std::string ==...
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2020-03-27
Rupert Swarbrick
Add support for SystemVerilog-style `define to Verilog...
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