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tests/mmu: Update to use correct MSR values
2020-08-20 Paul Mackerrastests/mmu: Update to use correct MSR values
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-07 Paul Mackerrascore: Implement BCD Assist instructions addg6s, cdtbcd...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the wait instruction as a no-op
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the reserved no-op instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the addex instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the maddhd, maddhdu and maddld instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the cmpeqb and cmprb instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the bpermd instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the setb instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the mcrxrx instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrascore: Implement the TAR register and the bctar instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasexecute1: Use r.<field> not v.<field> in countzero...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasexecute1: Take an extra cycle for OE=1 multiply instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasmultiplier: Generalize interface to the multiplier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Better expression for store data formatting
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Further tweaks to improve synthesis with...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Ease timing on wishbone data and byte selects
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdecode1: Fix formatting
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Separate address calculation for MMU to...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Generate busy signal earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Output separate done-without-error and error...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Ease timing on calculation of acks remaining
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Improve timing of valid/done outputs
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrascore: Don't generate logic for log data when LOG_LENGTH = 0
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrascountzero: Faster algorithm for count leading/trailing...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul MackerrasMMU: Improve timing of done signal back to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Remove dependency of r1.wb.adr/dat/sel on...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Update TLB PLRU one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasloadstore1: Eliminate two_dwords variable
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasexecute1: Ease timing on redirect_nia
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Do PLRU update one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasicache: Do PLRU update one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrasexecute1: Do forwarding of the CR result to the next...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrasexecute1: Add latch to redirect path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerraslogical: Only do output inversion for OP_AND, OP_OR...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrascore: Implement CFAR register
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasexecute1: Reduce width of the result mux to help timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrascore: Implement a simple branch predictor
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasdecode1: Improve timing for slow SPR decode path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-14 Paul Mackerrasdecode1: Add a stash buffer to the output
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce back-to-back store latency from 3 cycles...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmmu: Take an extra cycle to do TLB invalidations
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce latencies and improve timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdecode: Work out ispr1/ispr2 in parallel with decode...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Reduce busy cycles
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Complete mfspr/mtspr a cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Use a busy signal rather than a stall
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasicache: Improve latencies when reloading cache lines
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Use DSP48 slices for multiplication on Xilinx...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Move selection of result bits into execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Double the dcache and icache sizes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul MackerrasAdd core logging
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasscripts/mw_debug: Make progress counts display on one...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrastests/xics: Fix assumption that interrupts happen immediately
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasregister_file: Report value being written before asserting...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul Mackerrasdecode2: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul Mackerrasdecode1: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul Mackerrasdecode1: Make ld/std and lwa not be single-issue
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-15 Paul Mackerrasdcache: Fix bug in store hit after dcbz case
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-14 Paul Mackerrassoc: Work around compile error with ghdl 0.37-dev
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-14 Paul MackerrasMerge branch 'mmu'
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement reading of the process table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/mmu: Add a test of PTE refetching on permission...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/mmu: Add a test for dcbz with translation on
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement slbia as a dTLB/iTLB flush
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasDecode tlbiel as tlbie
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/privileged: Update for instruction translation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests: mmu: Add tests for instruction translation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Do radix page table walks on iTLB misses
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd TLB to icache
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests: Add a test for the MMU radix page table walks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Remove software-loaded dTLB mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Refetch PTE on access fault
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement data segment interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement radix page table machinery
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd framework for implementing an MMU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement access permission checks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement data storage interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdcache: Implement data TLB
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasPass mtspr/mfspr to MMU-related SPRs down to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasmw_debug: Add support for reading GSPRs and writing...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdebug: Provide a way to examine GPRs, fast SPRs and MSR
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImprove architectural compliance of mfspr and mtspr
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdecode1: Implement eieio as a nop
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement the extswsli instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerrasexecute1: Fix interrupt delivery during slow instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerraswishbone_debug_master: Fix address auto-increment for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul MackerrasMerge remote-tracking branch 'remotes/origin/master'
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2020-05-06 Paul Mackerrasdcache: Don't assert on dcbz cache hit
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasChange the default cross compiler prefix to powerpc64le...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasMakefile: fix typo
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul Mackerrastests: Add a test for privileged instruction interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasdcache: Implement the dcbz instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul MackerrasPlumb insn_type through to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Generate privileged instruction interrupts...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Improve architecture compliance of MSR and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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