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mem: Avoid setting markPending if not needed
2015-09-04 Andreas Hanssonmem: Avoid setting markPending if not needed
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2015-09-04 Andreas Hanssonmem: Tidy up CacheSet
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2015-09-04 Andreas Hanssonmem: Tidy up the snoop state-transition logic
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2015-09-04 Andreas Hanssonsim: Fix time unit in abort message
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2015-08-24 Andreas Hanssonmem: Revert requirement on packet addr/size always...
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2015-08-21 Andreas Hanssonmem: Reflect that packet address and size are always...
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2015-08-21 Andreas Hanssonarm, mem: Remove unused CLEAR_LL request flag
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2015-08-21 Andreas Hanssonmem: Remove unused cache squash functionality
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2015-08-21 Andreas Hanssonmem: Add explicit Cache subclass and make BaseCache...
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2015-08-21 Andreas Hanssonruby: Move Rubys cache class from Cache.py to RubyCache.py
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2015-08-21 Andreas Hanssonmem: Move cache_impl.hh to cache.cc
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2015-08-21 Andreas Hanssoncpu: Move invldPid constant from Request to BaseCPU
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2015-08-07 Andreas Hanssonmem: Remove extraneous acquire/release flags and attributes
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2015-08-05 Andreas Hanssonutil: Enable DRAM sweep to print power and efficiency
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2015-08-05 Andreas Hanssonstats: Reflect current behaviour
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2015-07-30 Andreas Hanssonstats: Update stats for clean eviction addition
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2015-07-30 Andreas Hanssonmem: Add missing clean eviction on uncacheable access
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2015-07-30 Andreas Hanssonmem: Remove unused RequestCause in cache
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2015-07-30 Andreas Hanssonmem: Transition away from isSupplyExclusive for writebacks
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2015-07-30 Andreas Hanssonmem: Tidy up CacheBlk class
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2015-07-30 Andreas Hanssonmem: Tidy up packet
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2015-07-30 Andreas Hanssonstats: Bump stats to match current behaviour
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2015-07-30 Andreas Hanssoncpu: Fix issue identified by UBSan
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2015-07-13 Andreas Hanssonmem: Fix (ab)use of emplace to avoid temporary object...
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2015-07-13 Andreas Hanssonmem: Updated DRAMSim2 wrapper to new drain API
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2015-07-03 Andreas Hanssonstats: Update stats for cache, crossbar and DRAM changes
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2015-07-03 Andreas Hanssonmem: Increase the default buffer sizes for the DDR4...
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2015-07-03 Andreas Hanssonmem: Avoid DRAM write queue iteration for merging and...
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2015-07-03 Andreas Hanssonmem: Delay responses in the crossbar before forwarding
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2015-07-03 Andreas Hanssonmem: Remove redundant is_top_level cache parameter
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2015-07-03 Andreas Hanssonmem: Split WriteInvalidateReq into write and invalidate
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2015-07-03 Andreas Hanssonmem: Add ReadCleanReq and ReadSharedReq packets
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2015-07-03 Andreas Hanssonmem: Allow read-only caches and check compliance
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2015-07-03 Andreas Hanssonmem: Convert Request static const flags to enums
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2015-07-03 Andreas Hanssonutil: Remove DRAMPower trace script
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2015-07-03 Andreas Hanssonscons: Bump compiler requirement to gcc >= 4.7 and...
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2015-06-09 Andreas Hanssonmem: Fix snoop packet data allocation bug
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2015-06-09 Andreas Hanssonscons: Allow GNU assembler version strings with hyphen
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2015-05-26 Andreas Hanssonarm, stats: Update stats to reflect reduction in misc...
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2015-05-26 Andreas Hanssonbase: Allow multiple interleaved ranges
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2015-05-26 Andreas Hanssonstats: Update MinorCPU regressions after accounting fix
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2015-05-26 Andreas Hanssonruby: Deprecation warning for RubyMemoryControl
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2015-05-15 Andreas Hanssonarm: Identify table-walker requests
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2015-05-15 Andreas Hanssonmisc: Appease gcc 5.1
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2015-05-15 Andreas Hanssonconfig: Use null memory for DRAM sweep script
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2015-05-05 Andreas Hanssonstats, arm: Update stats for missing FPEXC.EN check
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2015-05-05 Andreas Hanssonarm: Add missing FPEXC.EN check
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2015-05-05 Andreas Hanssonstats: Update stats to reflect cache changes
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2015-05-05 Andreas Hanssonarm: Remove unnecessary boot uncachability
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2015-05-05 Andreas Hanssonmem: Snoop into caches on uncacheable accesses
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2015-05-05 Andreas Hanssonarch, cpu: Do not forward snoops to table walker
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2015-05-05 Andreas Hanssonmem: Pass shared downstream through caches
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2015-05-05 Andreas Hanssonmem: Add missing stats update for uncacheable MSHRs
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2015-05-05 Andreas Hanssonmem: Tidy up BaseCache parameters
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2015-05-05 Andreas Hanssoncpu: Work around gcc 4.9 issues with Num_OpClasses
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2015-05-05 Andreas Hanssonstats: Bring regression stats in line with actual behaviour
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2015-04-24 Andreas Hanssonmisc: Appease gcc 5.1 without moving GDB_REG_BYTES
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2015-04-23 Andreas Hanssonmisc: Appease gcc 5.1
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2015-04-20 Andreas Hanssoncpu: Remove the InOrderCPU from the tree
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2015-04-20 Andreas Hanssonconfig: Remove memory aliases and rely on class name
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2015-03-27 Andreas Hanssonarm, configs: Do not forward snoops from I cache
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2015-03-27 Andreas Hanssonmem: Allocate cache writebacks before new MSHRs
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2015-03-27 Andreas Hanssonmem: Cleanup flow for uncacheable accesses
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2015-03-27 Andreas Hanssonmem: Ignore uncacheable MSHRs when finding matches
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2015-03-27 Andreas Hanssonmem: Remove redundant allocateUncachedReadBuffer in...
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2015-03-27 Andreas Hanssonmem: Modernise MSHR iterators to C++11
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2015-03-27 Andreas Hanssontests: Update stats for cache block alignment
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2015-03-27 Andreas Hanssonmem: Align all MSHR entries to block boundaries
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2015-03-26 Andreas Hanssoncpu: Fix InstPBTrace inheritance
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2015-03-23 Andreas Hanssonmem: Tidy up Request
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2015-03-23 Andreas Hanssontests: Final reclassification of quick regressions
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2015-03-19 Andreas Hanssontests: Recategorise regressions based on run time
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2015-03-19 Andreas Hanssonconfig: Add soak test for memtest.py
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2015-03-19 Andreas Hanssonmem: Use emplace front/back for deferred packets
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2015-03-19 Andreas Hanssonconfig: Fix DRAM rank option in sweep script
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2015-03-19 Andreas Hanssontests: Bump timeout to 5 hours
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2015-03-02 Andreas Hanssonstats: Update stats to reflect cache and interconnect...
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2015-03-02 Andreas Hanssonmem: Unify all cache DPRINTF address formatting
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2015-03-02 Andreas Hanssonmem: Fix cache MSHR conflict determination
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2015-03-02 Andreas Hanssonmem: Add byte mask to Packet::checkFunctional
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2015-03-02 Andreas Hanssonmem: Move crossbar default latencies to subclasses
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2015-03-02 Andreas Hanssonarm: Share a port for the two table walker objects
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2015-03-02 Andreas Hanssonmem: Tidy up the cache debug messages
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2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
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2015-03-02 Andreas Hanssontests: Run regression timeout as foreground
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2015-02-16 Andreas Hanssonconfig: Add memcheck stress test
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2015-02-16 Andreas Hanssoncpu: TrafficGen sinks snoops without complaining
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2015-02-16 Andreas Hanssondev: Fix undefined behaviuor in i8254xGBe
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2015-02-16 Andreas Hanssonmem: mmap the backing store with MAP_NORESERVE
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2015-02-16 Andreas Hanssonmem: Use the range cache for lookup as well as access
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2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
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2015-02-11 Andreas Hanssonconfig: Revamp memtest to allow testers on any level
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2015-02-11 Andreas Hanssonstats: Bump the MemTest regression stats
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2015-02-11 Andreas Hanssoncpu: Tidy up the MemTest and make false sharing more...
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2015-02-11 Andreas Hanssonbase: Do not dereference NULL in CompoundFlag creation
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2015-02-03 Andreas Hanssonmem: Clarify express snoop behaviour
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2015-02-03 Andreas Hanssonmem: Clarify cache behaviour for pending dirty responses
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2015-02-03 Andreas Hanssonconfig: Add XOR hashing to the DRAM channel interleaving
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2015-02-03 Andreas Hanssonbase: Add XOR-based hashed address interleaving
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2015-02-03 Andreas Hanssonconfig: Adjust DRAM channel interleaving defaults
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