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Ignore merging past ffs that we are not properly merging
2022-04-29
Miodrag Milanovic
Ignore merging past ffs that we are not properly merging
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2022-04-25
Miodrag Milanović
Merge pull request #3290 from mpasternacki/bugfix/freebsd...
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2022-04-25
Miodrag Milanović
Merge pull request #3289 from YosysHQ/micko/sim_improve
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2022-04-22
Miodrag Milanovic
Match $anyseq input if connected to public wire
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2022-04-22
Miodrag Milanovic
Treat $anyseq as input from FST
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2022-04-22
Miodrag Milanovic
Ignore change on last edge
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2022-04-22
Miodrag Milanovic
Last sample from input does not represent change
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2022-04-22
Miodrag Milanovic
latches are always set to zero
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2022-04-22
Miodrag Milanovic
If not multiclock, output only on clock edges
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2022-04-22
Miodrag Milanovic
Set init state for all wires from FST and set past
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2022-04-22
Miodrag Milanovic
Fix multiclock for btor2 witness
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2022-04-18
Miodrag Milanović
Merge pull request #3280 from YosysHQ/micko/fix_readaiw
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2022-04-18
Miodrag Milanovic
Update abc
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2022-04-18
Miodrag Milanovic
verific: allow memories to be inferred in loops (vhdl)
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2022-04-18
Miodrag Milanović
Merge pull request #3282 from nakengelhardt/verific_loop_rams
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2022-04-15
Miodrag Milanovic
Fix reading aiw from other solvers
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2022-04-08
Miodrag Milanović
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
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2022-04-08
Miodrag Milanovic
Use wrap_async_control_gate if ff is fine
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2022-04-08
Miodrag Milanović
Merge pull request #3273 from modwizcode/fix-build
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2022-04-05
Miodrag Milanovic
Reorder steps in -auto-top to fix synth command, fixes...
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2022-04-05
Miodrag Milanovic
Next dev cycle
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2022-04-05
Miodrag Milanovic
Release version 0.16
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2022-04-04
Miodrag Milanovic
Update CHANGELOG and manual
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2022-04-04
Miodrag Milanović
Merge pull request #3265 from YosysHQ/micko/sim_improvements
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2022-04-02
Miodrag Milanovic
past_ad initial value setting
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2022-04-02
Miodrag Milanovic
setInitState can be only one altering values
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2022-04-02
Miodrag Milanovic
Set past_d value for init state
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2022-04-01
Miodrag Milanović
Merge pull request #3263 from YosysHQ/micko/clk2ff_init
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2022-04-01
Miodrag Milanovic
Set init values for wrapped async control signals
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2022-04-01
Miodrag Milanović
Merge pull request #3262 from YosysHQ/micko/verific_hiernet
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2022-04-01
Miodrag Milanovic
Preserve internal wires for external nets
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2022-03-31
Miodrag Milanović
Merge pull request #3256 from YosysHQ/micko/aiw_multiclock
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2022-03-31
Miodrag Milanovic
Support memories in aiw and multiclock
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2022-03-30
Miodrag Milanović
Merge pull request #3259 from YosysHQ/micko/verific_valgrind
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2022-03-30
Miodrag Milanovic
Fix valgrind tests when using verific
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2022-03-30
Miodrag Milanović
Merge pull request #3260 from YosysHQ/micko/proper_scopename
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2022-03-30
Miodrag Milanovic
Proper scope naming from FST
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2022-03-30
Miodrag Milanović
Merge pull request #3250 from YosysHQ/micko/verific_consistent
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2022-03-29
Miodrag Milanović
Merge pull request #3258 from jix/fix-no-assertions
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2022-03-28
Miodrag Milanović
Update URL to zlib
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2022-03-26
Miodrag Milanovic
Properly mark modules imported
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2022-03-25
Miodrag Milanović
Merge pull request #3249 from YosysHQ/micko/no_startoffset
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2022-03-25
Miodrag Milanovic
Import verific netlist in consistent order
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2022-03-25
Miodrag Milanovic
Add -no-startoffset option to write_aiger
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2022-03-24
Miodrag Milanović
Merge pull request #3243 from nakengelhardt/fix_aiw_comment
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2022-03-22
Miodrag Milanovic
Update abc with latest fix
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-18
Miodrag Milanovic
More verbose warnings
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2022-03-17
Miodrag Milanović
Merge pull request #3236 from YosysHQ/micko/tb_initial
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2022-03-16
Miodrag Milanovic
Recognize registers and set initial state for them...
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2022-03-16
Miodrag Milanovic
Update sim help message.
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2022-03-14
Miodrag Milanović
Merge pull request #3232 from YosysHQ/micko/fst2tb
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2022-03-14
Miodrag Milanovic
Added fst2tb pass for generating testbench
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2022-03-14
Miodrag Milanovic
Proper example code
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2022-03-11
Miodrag Milanović
Merge pull request #3229 from YosysHQ/micko/sim_date
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2022-03-11
Miodrag Milanović
Merge pull request #3222 from zachjs/prune-linux-ci
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2022-03-11
Miodrag Milanović
Merge pull request #3228 from YosysHQ/micko/disable_tests
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2022-03-11
Miodrag Milanovic
Add date parameter to enable full date/time and version...
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2022-03-11
Miodrag Milanović
Merge pull request #3226 from YosysHQ/micko/btor2witness
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2022-03-11
Miodrag Milanovic
FstData already do conversion to VCD
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2022-03-11
Miodrag Milanovic
Support cell name in btor witness file
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2022-03-11
Miodrag Milanovic
handle state names of $anyconst and $anyseq
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2022-03-11
Miodrag Milanovic
Proper write of memory data
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2022-03-10
Miodrag Milanovic
Disable tests on most of platforms
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2022-03-09
Miodrag Milanovic
Start work on memory init
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2022-03-09
Miodrag Milanovic
Fixes and error check
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2022-03-07
Miodrag Milanovic
cleanup
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2022-03-07
Miodrag Milanovic
Error checks for aiger witness
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2022-03-07
Miodrag Milanovic
btor2 witness co-simulation
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2022-03-07
Miodrag Milanović
Merge pull request #3210 from rqou/json-signed
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2022-03-04
Miodrag Milanović
Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id
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2022-03-04
Miodrag Milanović
Merge pull request #3206 from YosysHQ/micko/quote_remove
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2022-03-04
Miodrag Milanović
Merge pull request #3207 from nakengelhardt/json_escape_quotes
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2022-03-04
Miodrag Milanovic
Next dev cycle
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2022-03-04
Miodrag Milanovic
Release version 0.15
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2022-03-04
Miodrag Milanovic
Update ABC
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2022-03-04
Miodrag Milanovic
Update documentation
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2022-03-04
Miodrag Milanović
Merge pull request #3219 from YosysHQ/micko/quick_vcd
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2022-03-04
Miodrag Milanović
Merge pull request #3220 from YosysHQ/claire/simstuff
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2022-03-02
Miodrag Milanovic
Add option to ignore X only signals in output
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2022-03-02
Miodrag Milanovic
Write simulation files after simulation is performed
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2022-03-02
Miodrag Milanovic
Update CHANGELOG
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2022-03-02
Miodrag Milanovic
Cleanup
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2022-02-28
Miodrag Milanovic
Refactor sim output writers
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2022-02-28
Miodrag Milanovic
Quick fix
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2022-02-28
Miodrag Milanovic
VCD reader support by using external tool
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2022-02-28
Miodrag Milanović
Merge pull request #3216 from YosysHQ/claire/simstuff
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2022-02-27
Miodrag Milanovic
Support extended aiw format
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2022-02-25
Miodrag Milanovic
Fix for last clock edge data
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2022-02-21
Miodrag Milanović
Merge pull request #3203 from YosysHQ/micko/sim_ff
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2022-02-21
Miodrag Milanovic
Fix handling of ce_over_srst
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2022-02-18
Miodrag Milanovic
Changed error message
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2022-02-18
Miodrag Milanovic
Added AIGER witness file co simulation
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2022-02-18
Miodrag Milanovic
simplify logic of handling flip-flops and latches
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2022-02-17
Miodrag Milanovic
Review cleanup
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2022-02-16
Miodrag Milanovic
Remove quotes if any from attribute
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2022-02-16
Miodrag Milanovic
test dlatchsr and adlatch
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2022-02-16
Miodrag Milanovic
Added test cases
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2022-02-16
Miodrag Milanovic
Add support for various ff/latch cells simulation
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