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Add -hidden option to submod
2019-11-27
Eddie Hung
Add -hidden option to submod
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2019-11-26
Eddie Hung
Update docs with bullet points
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2019-11-26
Eddie Hung
Move \init from source wire to submod if output port
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2019-11-26
Eddie Hung
Add testcase where \init is copied
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2019-11-23
Eddie Hung
Remove redundant flatten
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2019-11-23
Eddie Hung
submod to bitty rather bussy, for bussy wires used...
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2019-11-23
Eddie Hung
Stray dump
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2019-11-23
Eddie Hung
Constant driven signals are also an input to submodules
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2019-11-23
Eddie Hung
Add another test with constant driver
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2019-11-23
Eddie Hung
Oops
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2019-11-23
Eddie Hung
Cleanup spacing
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2019-11-23
Eddie Hung
sigmap(wire) should inherit port_output status of POs
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2019-11-23
Eddie Hung
Add testcase
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2019-10-08
Eddie Hung
Revert "Add test that is expecting to fail"
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2019-10-08
Eddie Hung
Revert "Be mindful that sigmap(wire) could have dupes...
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2019-10-05
Eddie Hung
Missing 'accept' at end of ice40_wrapcarry, spotted...
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2019-10-05
Eddie Hung
Missed this
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2019-10-05
Eddie Hung
Add comment on why we have to match for clock-enable...
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2019-10-05
Eddie Hung
Add note on pattern detector
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2019-10-05
Eddie Hung
Add comment on why partial multipliers are 18x18
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp_cascade
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2019-10-05
Eddie Hung
Improve comments for xilinx_dsp_CREG
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2019-10-05
Eddie Hung
Fix comment
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2019-10-05
Eddie Hung
Restore optimisation for sigM.empty()
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2019-10-05
Eddie Hung
Retry on fixing TODOs
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2019-10-05
Eddie Hung
Revert "Fix TODOs"
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2019-10-05
Eddie Hung
More comments, cleanup
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2019-10-05
Eddie Hung
Fix TODOs
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2019-10-05
Eddie Hung
Consistency
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp
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2019-10-05
Eddie Hung
Fix typo in check_label()
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Add temporary `abc9 -nomfs` and use for `synth_xilinx...
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2019-10-05
Eddie Hung
Remove DSP48E1 from *_cells_xtra.v
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2019-10-04
Eddie Hung
Fix xilinx_dsp for unsigned extensions
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2019-10-04
Eddie Hung
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true...
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2019-10-04
Eddie Hung
Add Const::{begin,end,empty}()
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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2019-10-04
Eddie Hung
Panic over. Model was elsewhere. Re-arrange for consistency
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2019-10-04
Eddie Hung
Oops
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2019-10-04
Eddie Hung
Ohmilord this wasn't added all this time!?!
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2019-10-04
Eddie Hung
Add -async2sync to help text as per @daveshah1
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2019-10-03
Eddie Hung
Use `sat -tempinduct` and comments for why equiv_opt...
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2019-10-03
Eddie Hung
Restore part of doc
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2019-10-03
Eddie Hung
Disable equiv check for ice40 latches
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2019-10-03
Eddie Hung
Add new -async2sync option
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2019-10-03
Eddie Hung
Use equiv_opt -async2sync for xilinx
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2019-10-03
Eddie Hung
Revert "equiv_opt to call async2sync when not -multiclock...
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2019-10-03
Eddie Hung
Revert "Update doc for equiv_opt"
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2019-10-03
Eddie Hung
Fix broken CI, check reset even for constants, trim...
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2019-10-03
Eddie Hung
Fix test
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2019-10-03
Eddie Hung
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
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2019-10-03
Eddie Hung
Update test
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2019-10-03
Eddie Hung
Refactor peepopt_dffmux and be sensitive to \init when...
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2019-10-03
Eddie Hung
Add test
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2019-10-03
Eddie Hung
log_dump() to support State enum
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2019-10-02
Eddie Hung
Be mindful that sigmap(wire) could have dupes when...
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2019-10-02
Eddie Hung
Add test that is expecting to fail
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2019-10-02
Eddie Hung
Also rename cells with _TECHMAP_REPLACE_. prefix, as...
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2019-10-02
Eddie Hung
Extend test with renaming cells with prefix too
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2019-10-01
Eddie Hung
equiv_opt with -assert
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2019-10-01
Eddie Hung
Update resource count for alu.ys
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2019-10-01
Eddie Hung
Add test
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2019-10-01
Eddie Hung
techmap wires named _TECHMAP_REPLACE_.<identifier>...
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2019-09-30
Eddie Hung
Add quick test
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2019-09-30
Eddie Hung
Add -select option to aigmap
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2019-09-30
Eddie Hung
Fix typo
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2019-09-30
Eddie Hung
Move $x to end as per 7f0eec8
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2019-09-30
Eddie Hung
Update fsm.ys resource count
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2019-09-30
Eddie Hung
Merge branch 'SergeyDegtyar/ecp5' of https://github...
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2019-09-30
Eddie Hung
Fix for svinterfaces
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2019-09-30
Eddie Hung
module->derive() to be lazy and not touch ast if already...
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2019-09-30
Eddie Hung
Update doc for equiv_opt
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2019-09-28
Eddie Hung
Fix box name
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2019-09-27
Eddie Hung
Re-order
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2019-09-27
Eddie Hung
Missing (* mul2dsp *) for sliceB
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2019-09-27
Eddie Hung
equiv_opt to call async2sync when not -multiclock like...
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2019-09-27
Eddie Hung
Ooops AREG and BREG to default to -1
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2019-09-26
Eddie Hung
Update doc with max cascade chain of 20
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2019-09-26
Eddie Hung
Do not always zero out C (e.g. during cascade breaks)
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2019-09-26
Eddie Hung
Update doc
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2019-09-26
Eddie Hung
Zero out ports
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2019-09-26
Eddie Hung
xilinx_dsp_cascade to also cascade AREG and BREG
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2019-09-26
Eddie Hung
Try recursive pmgen for P cascade
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2019-09-26
Eddie Hung
Missing an '&'
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2019-09-26
Eddie Hung
Combine 'flatten' & 'coarse' labels in synth_ecp5 so...
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2019-09-26
Eddie Hung
Typo
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2019-09-26
Eddie Hung
CREG to check for \keep
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2019-09-26
Eddie Hung
Remove newline
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2019-09-26
Eddie Hung
select once
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2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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2019-09-26
Eddie Hung
mul2dsp.v slice names
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2019-09-26
Eddie Hung
Do not die if DSP48E1.P has no users (would otherwise...
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2019-09-26
Eddie Hung
Reject if (* init *) present
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2019-09-26
Eddie Hung
Remove unnecessary check for A_SIGNED != B_SIGNED;...
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2019-09-26
Eddie Hung
Revert "Remove _TECHMAP_CELLTYPE_ check since all ...
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2019-09-26
Eddie Hung
Revert "No need for $__mul anymore?"
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2019-09-26
Eddie Hung
Rework xilinx_dsp postAdd for new wreduce call
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2019-09-26
Eddie Hung
Only wreduce on t:$add
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2019-09-25
Eddie Hung
Remove _TECHMAP_CELLTYPE_ check since all $mul
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