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Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
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2019-04-22
Eddie Hung
Update help message
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2019-04-22
Eddie Hung
Move 'shregmap -tech xilinx' into map_cells
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-21
Eddie Hung
Tidy up, fix for -nosrl
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2019-04-21
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Eddie Hung
Add comments
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2019-04-21
Eddie Hung
Use new pmux2shiftx from #944, remove my old attempt
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shiftx...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-20
Eddie Hung
Merge remote-tracking branch 'origin' into xc7srl
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2019-04-19
Eddie Hung
Spelling fixes
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2019-04-19
Eddie Hung
Revert "write_json to not write contents (cells/wires...
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2019-04-18
Eddie Hung
Merge pull request #917 from YosysHQ/eddie/fix_retime
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2019-04-18
Eddie Hung
write_json to not write contents (cells/wires) of whiteboxes
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2019-04-18
Eddie Hung
Ignore 'whitebox' attr in flatten with "-wb" option
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2019-04-18
Eddie Hung
Fix abc's remap_name to not ignore [^0-9] when extracting sid
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2019-04-18
Eddie Hung
ABC to call retime all the time
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2019-04-18
Eddie Hung
Revert "synth_* with -retime option now calls abc with...
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2019-04-18
Eddie Hung
Merge branch 'master' into eddie/fix_retime
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2019-04-16
Eddie Hung
Add MUXCY and XORCY to cells_box.v
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2019-04-16
Eddie Hung
Fix wire numbering
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2019-04-16
Eddie Hung
Do not put constants into output_bits
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2019-04-16
Eddie Hung
Remove write_verilog call
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2019-04-16
Eddie Hung
Fix spacing
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-16
Eddie Hung
Re-enable partsel.v test
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2019-04-16
Eddie Hung
abc9 to call "setundef -zero" behaving as for abc
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2019-04-16
Eddie Hung
NULL check before use
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2019-04-16
Eddie Hung
WIP for box support
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2019-04-16
Eddie Hung
ABC to read_box before reading netlist
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2019-04-16
Eddie Hung
Make cells.box whiteboxes not blackboxes
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2019-04-16
Eddie Hung
read_verilog cells_box.v before techmap
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2019-04-16
Eddie Hung
Merge pull request #939 from YosysHQ/revert895
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2019-04-16
Eddie Hung
synth_xilinx: before abc read +/xilinx/cells_box.v
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2019-04-16
Eddie Hung
Add +/xilinx/cells_box.v containing models for ABC...
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2019-04-16
Eddie Hung
For 'stat' do not count modules with abc_box_id
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2019-04-16
Eddie Hung
Do not call abc on modules with abc_box_id attr
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2019-04-16
Eddie Hung
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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2019-04-16
Eddie Hung
Revert #895
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2019-04-16
Eddie Hung
Use abc_box_id
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2019-04-16
Eddie Hung
Check abc_box_id attr
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2019-04-16
Eddie Hung
Add abc_box_id attribute to MUXF7/F8 cells
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-16
Eddie Hung
Merge pull request #937 from YosysHQ/revert-932-eddie...
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2019-04-16
Eddie Hung
Revert "Recognise default entry in case even if all...
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2019-04-15
Eddie Hung
Merge pull request #936 from YosysHQ/README-fix-quotes
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2019-04-13
Eddie Hung
Forgot backslashes
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2019-04-13
Eddie Hung
Handle __dummy_o__ and __const[01]__ in read_aiger...
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2019-04-13
Eddie Hung
abc to ignore __dummy_o__ and __const[01]__ when re...
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2019-04-13
Eddie Hung
Output __const0__ and __const1__ CIs
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2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-13
Eddie Hung
Fix inout handling for -map option
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2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Use -map instead of -symbols for aiger
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2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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2019-04-12
Eddie Hung
Also cope with duplicated CIs
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2019-04-12
Eddie Hung
WIP
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2019-04-12
Eddie Hung
Comment out
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2019-04-12
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-12
Eddie Hung
Cope with an output having same name as an input (i...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Eddie Hung
PI before CI
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-11
Eddie Hung
Fix ordering of when to insert zero index
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
More unused
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
Remove unused
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2019-04-11
Eddie Hung
Fixes
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2019-04-11
Eddie Hung
WIP
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2019-04-11
Eddie Hung
Spelling fixes
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases covered...
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2019-04-11
Eddie Hung
Fix cells_map.v some more
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2019-04-11
Eddie Hung
More fine tuning
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2019-04-11
Eddie Hung
Fix cells_map.v
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2019-04-11
Eddie Hung
Fix typo
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2019-04-11
Eddie Hung
Juggle opt calls in synth_xilinx
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2019-04-11
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
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2019-04-11
Eddie Hung
WIP for cells_map.v -- maybe working?
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2019-04-10
Eddie Hung
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
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2019-04-10
Eddie Hung
Fix for when B_SIGNED = 1
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2019-04-10
Eddie Hung
Update doc for synth_xilinx
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2019-04-10
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-10
Eddie Hung
parse_aiger() to rename all $lut cells after "clean"
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2019-04-10
Eddie Hung
ff_map.v after abc
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2019-04-10
Eddie Hung
Tidy up
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2019-04-10
Eddie Hung
Move map_cells to before map_luts
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2019-04-10
Eddie Hung
WIP for $shiftx to wide mux
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2019-04-10
Eddie Hung
Update LUT delays
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2019-04-10
Eddie Hung
synth_* with -retime option now calls abc with -D 1...
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2019-04-10
Eddie Hung
Revert "abc -dff now implies "-D 0" otherwise retiming...
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2019-04-10
Eddie Hung
Revert ""&nf -D 0" fails => use "-D 1" instead"
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