git.libre-soc.org Git - yosys.git/search

2017-10-02	dh73	Tested and working altsyncarm without init files	commit \| commitdiff \| tree
2017-10-01	dh73	Fixed wrong declaration in Verilog backend	commit \| commitdiff \| tree
2017-10-01	dh73	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...	commit \| commitdiff \| tree
2017-04-06	dh73	Add initial support for both MAX10 and Cyclone IV ...	commit \| commitdiff \| tree