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Complete the formal proof of the pseudo dual port SRAM
2021-03-11
Cesar Strauss
Bring a few test cases from test_caller_64.py
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2021-03-11
Cesar Strauss
Test case for two successive SV instructions
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2021-03-09
Cesar Strauss
Enable VL==0 vector instruction skip test case
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2021-03-09
Cesar Strauss
Add some extra debug traces to the GTKWave document
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2021-03-09
Cesar Strauss
Create a new signal for the Simulator to wait on
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2021-03-08
Cesar Strauss
Remove the unused internal insn_done signal
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2021-03-08
Cesar Strauss
Fix argument order to match function declaration
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2021-03-07
Cesar Strauss
Fix missing NIA update on ISACaller
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2021-03-07
Cesar Strauss
Merge WAIT_RESET into INSN_FETCH on the Issue FSM
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2021-03-07
Cesar Strauss
Implement the VL==0 loop
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2021-03-06
Cesar Strauss
Allow updating the PC and SVSTATE registers while stopped
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2021-03-06
Cesar Strauss
Enable the Simple-V loop test case
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2021-03-06
Cesar Strauss
Begin to implement the Simple-V loop
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2021-03-06
Cesar Strauss
Do not reset pc_changed and sv_changed at instruction end
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2021-03-06
Cesar Strauss
Make the raw opcode input port of the decoder stay...
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2021-03-05
Cesar Strauss
Move writing of the PC state register to the issue FSM
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2021-03-05
Cesar Strauss
Move the wait on "core stop" out of fetch, and into...
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2021-02-27
Cesar Strauss
Add traces for the new FSM
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2021-02-26
Cesar Strauss
Add a vector case with VL == 0
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2021-02-26
Cesar Strauss
Implement a decode/issue FSM between fetch and execute
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2021-02-22
Cesar Strauss
Fix typo when calculating PowerDecoder2.no_out_vec
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2021-02-21
Cesar Strauss
The field selection function was moved to nmutil.util
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2021-02-21
Cesar Strauss
Hide the register augmentation traces by default
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2021-02-21
Cesar Strauss
The new version of "sel" is smart enough to find a...
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2021-02-21
Cesar Strauss
Use the new selection field function from nmutil
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2021-02-21
Cesar Strauss
Use symbolic values as field sizes
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2021-02-21
Cesar Strauss
Replace all hardcoded shifts into RM by usage of SVP64RMFields
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2021-02-20
Cesar Strauss
Actually forward the field width to field_slice()
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2021-02-20
Cesar Strauss
Assemble the SV64 prefix from its subfields using SVP64Prefi...
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2021-02-20
Cesar Strauss
Fix more MSB0 issues in comments
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2021-02-20
Cesar Strauss
Replace more hardcoded constants with symbolic field...
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2021-02-17
Cesar Strauss
Use subfield bit selection to extract the RM SVP64...
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2021-02-17
Cesar Strauss
Replace MSB-i by symbolic subfield indices and selectors
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2021-02-17
Cesar Strauss
Add the SVSTATE traces to GTKWave to allow debugging...
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2021-02-17
Cesar Strauss
Initialize the core SVSTATE from the corresponding...
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2021-02-17
Cesar Strauss
Revert "Setup SVSTATE, from the test settings, at the...
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2021-02-17
Cesar Strauss
Add a function to select bits from a signal into a...
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2021-02-17
Cesar Strauss
Add a case for checking the EXTRA field and register...
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2021-02-17
Cesar Strauss
Add traces to debug SVP64 prefix decoding issues
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2021-02-17
Cesar Strauss
Setup SVSTATE, from the test settings, at the start
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2021-02-16
Cesar Strauss
Fix MSB0 issues for SVP64
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2021-02-15
Cesar Strauss
Simplify obtaining the PC from the register file
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2021-02-14
Cesar Strauss
Show traces for the register numbers of the current...
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2021-02-14
Cesar Strauss
Fix width of the "extra" input on the Extra decoder
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2021-02-14
Cesar Strauss
Fix conversion to MSB0
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2021-02-14
Cesar Strauss
Remove obsolete comment
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2021-02-13
Cesar Strauss
Fetch and decode the SVP64 prefix
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2021-02-13
Cesar Strauss
Check the PC value at the end of each instruction
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2021-02-13
Cesar Strauss
Skip vector test case, and add a scalar case
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2021-02-13
Cesar Strauss
Fix imports and whitespace
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2021-02-13
Cesar Strauss
Fix SVP64 translator to yield the unaltered instruction
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2021-02-06
Cesar Strauss
Fix whitespace
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2021-02-06
Cesar Strauss
Extract the fetch FSM out from the main FSM
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2021-02-01
Cesar Strauss
Add GTKWave document to test_issuer
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2021-01-31
Cesar Strauss
Fix loop test and enable it
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2021-01-01
Cesar Strauss
Add zero CR test case and fix comments
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2021-01-01
Cesar Strauss
Add test cases with rc=1
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2021-01-01
Cesar Strauss
Make all ports the same size, on the test ALU
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2021-01-01
Cesar Strauss
Add CR output port to test cases
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2021-01-01
Cesar Strauss
Add CR to the output data port
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2021-01-01
Cesar Strauss
Make output write enables independent of valid_o
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2021-01-01
Cesar Strauss
Move NOP test case earlier
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2021-01-01
Cesar Strauss
Disable data value output on NOP
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2021-01-01
Cesar Strauss
Add condition register (CR) output
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2020-12-31
Cesar Strauss
Implement and test NOP in the test ALU
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2020-12-31
Cesar Strauss
Don't use OP_NOP for zero-delay subtraction
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2020-12-31
Cesar Strauss
Test first input port being masked out
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2020-12-31
Cesar Strauss
Sign extend the second input port
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2020-12-31
Cesar Strauss
Test masked-out second input port
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2020-12-31
Cesar Strauss
Add sign extend to the Test ALU
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2020-12-31
Cesar Strauss
Show rdmaskn and wrmask in GTKWave
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2020-12-31
Cesar Strauss
Use the increment operator
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2020-12-31
Cesar Strauss
Add support for masked write operations
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2020-12-31
Cesar Strauss
Clarify reason for holding rdmaskn valid during the...
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2020-12-31
Cesar Strauss
Remove previous version of the CompUnit parallel unit...
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2020-12-31
Cesar Strauss
Only hold the decoder signals for one cycle, along...
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2020-12-30
Cesar Strauss
Test the rdmaskn control signal
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2020-12-29
Cesar Strauss
Remove left-over comments.
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2020-12-20
Cesar Strauss
Add support for CXXSim simulation
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2020-12-13
Cesar Strauss
Ignore formal verification output in the source directory
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2020-12-13
Cesar Strauss
Allow more test cases to be run with CXXSim
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2020-12-07
Cesar Strauss
Display the instruction type as a vector on cxxsim
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2020-12-06
Cesar Strauss
Whitespace
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2020-12-06
Cesar Strauss
Update GTKWave documents to work with latest cxxsim
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2020-12-05
Cesar Strauss
Write a GTKWave document to investigate why the proof...
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2020-12-05
Cesar Strauss
Use the DummyALU regspec and its corresponding OpSubset
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2020-11-28
Cesar Strauss
Fix signal names: go/rel -> go_i/rel_o
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2020-11-24
Cesar Strauss
Fix some typos and whitespace
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2020-11-24
Cesar Strauss
Port the DummyALU test case to the new parallel issuer
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2020-11-23
Cesar Strauss
Results are now a list, so "expected" should follow...
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2020-11-23
Cesar Strauss
Parameterize the issuer on the number of operands and...
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2020-11-22
Cesar Strauss
Refactor the ALU operation issuer into a class
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2020-11-22
Cesar Strauss
Port the ALU test case to the new parallel test style
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2020-11-22
Cesar Strauss
Add a GTKWave document to the ALU test case
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2020-11-19
Cesar Strauss
Separate input and output ports by color
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2020-11-19
Cesar Strauss
Explain the test cases
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2020-11-18
Cesar Strauss
Separate individual traces for each rel_o/go_i port
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2020-11-16
Cesar Strauss
Add a transaction counter to producers and consumers
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2020-11-15
Cesar Strauss
Implement ResultConsumer and port the Shifter unit...
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2020-11-14
Cesar Strauss
Move the DUT driver to within the test case process
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