| 2019-01-26 |
whitequark | test.compat: import tests from Migen as appropriate.
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commit | commitdiff | tree |
| 2019-01-26 |
whitequark | hdl.ast: fix shape calculation for *.
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commit | commitdiff | tree |
| 2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync...
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commit | commitdiff | tree |
| 2019-01-22 |
whitequark | lib.fifo: in FIFOInterface.read(), check readable on...
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commit | commitdiff | tree |
| 2019-01-22 |
whitequark | compat.genlib.fifo: adjust _FIFOInterface shim to not...
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commit | commitdiff | tree |
| 2019-01-22 |
whitequark | lib.fifo: fix typo in AsyncFIFO documentation.
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commit | commitdiff | tree |
| 2019-01-21 |
whitequark | lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
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commit | commitdiff | tree |
| 2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing...
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commit | commitdiff | tree |
| 2019-01-20 |
whitequark | compat.genlib.cdc: add missing import.
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commit | commitdiff | tree |
| 2019-01-20 |
whitequark | compat.genlib.cdc: add GrayCounter and GrayDecoder...
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commit | commitdiff | tree |
| 2019-01-20 |
whitequark | lib.coding: add GrayEncoder and GrayDecoder.
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commit | commitdiff | tree |
| 2019-01-20 |
whitequark | lib.coding: add width as attribute to all coders.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | lib.fifo: use memory in the FIFO model.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | lib.fifo: use model equivalence to simplify formal...
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | hdl.ast: implement shape for modulo operator.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | hdl.ast: add Value.implies.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | hdl.xfrm: mark internal registers used in lowering...
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | doc: update COMPAT_SUMMARY.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | fhdl.specials: add compatibility shim for Tristate.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | lib.fifo: fix simulation read/write methods to take...
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | lib.fifo: formally verify FIFO contract.
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commit | commitdiff | tree |
| 2019-01-19 |
whitequark | hdl.ast: give Assert and Assume their own src_loc.
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commit | commitdiff | tree |
| 2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | lib.fifo: add basic formal specification.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | formal: extract from toplevel module.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer.
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commit | commitdiff | tree |
| 2019-01-17 |
whitequark | hdl.ast: add Sample.
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commit | commitdiff | tree |
| 2019-01-16 |
whitequark | lib.fifo: port sync FIFO queues from Migen.
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commit | commitdiff | tree |
| 2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when tracer...
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commit | commitdiff | tree |
| 2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals...
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commit | commitdiff | tree |
| 2019-01-16 |
whitequark | back.rtlil: rename \sig$next to $next$sig.
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commit | commitdiff | tree |
| 2019-01-16 |
whitequark | Travis: install SymbiYosys and Yices2.
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commit | commitdiff | tree |
| 2019-01-15 |
whitequark | Unbreak 655d02d5.
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commit | commitdiff | tree |
| 2019-01-14 |
whitequark | lib.io: pass pin to platform.get_tristate().
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commit | commitdiff | tree |
| 2019-01-14 |
whitequark | hdl.ir: allow explicitly requesting flattening.
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commit | commitdiff | tree |
| 2019-01-14 |
whitequark | lib.io: lower to platform-independent tristate buffer.
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commit | commitdiff | tree |
| 2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS.
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commit | commitdiff | tree |
| 2019-01-13 |
whitequark | hdl.dsl: cases wider than switch test value are unreachable.
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commit | commitdiff | tree |
| 2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch...
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commit | commitdiff | tree |
| 2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals.
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commit | commitdiff | tree |
| 2019-01-13 |
whitequark | back.verilog: better error message if Yosys is not...
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commit | commitdiff | tree |
| 2019-01-08 |
whitequark | back.verilog: remove undriven check.
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commit | commitdiff | tree |
| 2019-01-02 |
whitequark | hdl.ast: allow slicing [n:n] into n-bit value.
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commit | commitdiff | tree |
| 2019-01-02 |
whitequark | back.rtlil: translate empty slices correctly.
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commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.ast: experimentally add Value._as_const.
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commit | commitdiff | tree |
| 2019-01-01 |
whitequark | back.rtlil: fix typo.
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commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.rec: include record name in error message.
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commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.rec: use a helpful error on unknown field reference.
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commit | commitdiff | tree |
| 2019-01-01 |
whitequark | hdl.mem: add DummyPort, for testing and verification.
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commit | commitdiff | tree |
| 2018-12-31 |
whitequark | back.rtlil: match shape of Array elements to ArrayProxy...
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commit | commitdiff | tree |
| 2018-12-31 |
whitequark | back.rtlil: fix typo.
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commit | commitdiff | tree |
| 2018-12-29 |
whitequark | lib.cdc: fix tests to actually run.
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commit | commitdiff | tree |
| 2018-12-29 |
whitequark | back.pysim: warn if simulation is not run.
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commit | commitdiff | tree |
| 2018-12-28 |
whitequark | hdl.rec: add basic record support.
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commit | commitdiff | tree |
| 2018-12-28 |
whitequark | tracer: factor out get_src_loc().
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commit | commitdiff | tree |
| 2018-12-27 |
whitequark | lib.coding: fix tests to actually run, and fix code...
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commit | commitdiff | tree |
| 2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing().
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commit | commitdiff | tree |
| 2018-12-27 |
whitequark | hdl.mem: add missing __all__.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | lib.coding: port from Migen.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | lib.cdc: add tests for MultiReg.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: forbid m.next= inside of FSM but outside of...
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: provide generated values for FSMs.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.ir: add an API for retrieving generated values...
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | examples: add an FSM usage example (UART receiver).
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: add signal decoder to FSM state signal.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | hdl.dsl: implement FSM.
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commit | commitdiff | tree |
| 2018-12-26 |
whitequark | back.rtlil: clarify $verilog_initial_trigger behavior...
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: unbreak d47c1f8a.
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.mem: allow omitting memory simulation logic.
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: use one $meminit cell, not one per word.
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty...
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commit | commitdiff | tree |
| 2018-12-24 |
whitequark | back.rtlil: always output negative values as two's...
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: emit dummy logic to work around Verilog...
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: do not translate empty fragments.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: only translate switch tests once.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: generate: guess file type from extension.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: fix swapped operands in mux codegen.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: new module, for basic design generaton/simulation.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat.genlib.fsm: fix naming for non-Signal LHS.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: flatten hierarchy based on memory accesses...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: factor out _merge_subfragment. NFC.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: implement LHSGroupAnalyzer.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: use nicer names for next_value/next_value_ce...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.mem: allow changing init value after creating memory.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.verilog: do not rename internal signals.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: fix confusing naming for memory port address...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: fix port propagation between siblings, in the...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: do not finalize native submodules twice.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: use more informative signal naming for ports.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: fix port propagation between siblings.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | compat: provide verilog.convert shim.
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commit | commitdiff | tree |
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