2021-05-18 |
Luke Kenneth Casson... | finally fix bpermd pseudocode, index was being treated...
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2021-05-18 |
Luke Kenneth Casson... | revert register reordering in ISACaller
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2021-05-18 |
Luke Kenneth Casson... | add os.makedirs on pyfnwriter output path
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2021-05-18 |
Luke Kenneth Casson... | add python function writer, takes Appendix v3.0B pseudocode...
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2021-05-17 |
Luke Kenneth Casson... | update reg sort order in ISACaller
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2021-05-17 |
Luke Kenneth Casson... | grr syntax incorrect, use <- operator not =
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2021-05-17 |
Luke Kenneth Casson... | mark RN as TODO
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2021-05-17 |
Luke Kenneth Casson... | must not add to read regs unless in the authorised...
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2021-05-17 |
Luke Kenneth Casson... | remove MISSING (theyre not), fix a couple of errors...
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2021-05-17 |
Luke Kenneth Casson... | add new RC reg to get pywriter to build
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2021-05-16 |
Luke Kenneth Casson... | update to 0.0.3
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2021-05-16 |
Luke Kenneth Casson... | document addition of pyfnwriter
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2021-05-16 |
Luke Kenneth Casson... | add NEWS update
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2021-05-16 |
Luke Kenneth Casson... | add fpcvt.mdwn pseudocode which calls new auto-generated...
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2021-05-16 |
Luke Kenneth Casson... | add new pyfnwriter command, converts v3.0B spec pseudocode...
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2021-05-16 |
Luke Kenneth Casson... | create compiler for general pseudo-code functions in...
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2021-05-16 |
Luke Kenneth Casson... | add function reader for appendix and other v3.0B pseudocode
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2021-05-16 |
Luke Kenneth Casson... | comments in fp convert, fix carry out, comment out...
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2021-05-15 |
Luke Kenneth Casson... | spelling
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2021-05-15 |
Luke Kenneth Casson... | move round_float to separate file
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2021-05-15 |
Luke Kenneth Casson... | add fpfromint.mdwn new file, to be used for FP conversion
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2021-05-15 |
Luke Kenneth Casson... | extra debug print
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2021-05-15 |
Luke Kenneth Casson... | whoops, FRC taken from FormX.FRB not FormA.FRC
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2021-05-15 |
Luke Kenneth Casson... | FP mul test, correct pseudocode to use FRC
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2021-05-15 |
Luke Kenneth Casson... | add minor_59.csv file, corrected, and power enums
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2021-05-15 |
Luke Kenneth Casson... | return result in FPXXX64 functions (whoops)
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2021-05-15 |
Luke Kenneth Casson... | when calling multi-arg function with regs, add to read...
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2021-05-15 |
Luke Kenneth Casson... | issue with sub-decoders
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2021-05-15 |
Luke Kenneth Casson... | add fadd/sub/mul/div to power_enums
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2021-05-15 |
Luke Kenneth Casson... | add FP basic arithmetic operations, pseudocode, fparith...
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2021-05-15 |
Luke Kenneth Casson... | comments
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2021-05-15 |
Luke Kenneth Casson... | add fcpsgn unit test
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2021-05-15 |
Luke Kenneth Casson... | add fnabs unit test
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commit | commitdiff | tree |
2021-05-15 |
Luke Kenneth Casson... | add fabs unit test
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2021-05-15 |
Luke Kenneth Casson... | add fp mv test, correct pseudocode
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2021-05-15 |
Luke Kenneth Casson... | whoops initialise FPRs from GPRs in ISACaller
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2021-05-15 |
Luke Kenneth Casson... | missed an assignment-copy for simple expressions
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2021-05-15 |
Luke Kenneth Casson... | add fmr test and associated decoder (optional with...
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2021-05-15 |
Luke Kenneth Casson... | add X-Form and A-Form to minor_63l and minor_63h csv...
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2021-05-15 |
Luke Kenneth Casson... | whoops need to reverse bits in minor_63l.csv to match...
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2021-05-15 |
Luke Kenneth Casson... | FP 63L/H ops need to add in extra 0/1 minor_63l.csv...
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2021-05-15 |
Luke Kenneth Casson... | add fp move opcodes to power_enums.py
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2021-05-15 |
Luke Kenneth Casson... | add new fp load / store with update unit test
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2021-05-15 |
Luke Kenneth Casson... | add FP store op names to power_enums.py opcode list
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2021-05-15 |
Luke Kenneth Casson... | whitespace on instruction mnemonics
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2021-05-15 |
Luke Kenneth Casson... | add FP LD/ST D-Form operations to major.csv
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2021-05-15 |
Luke Kenneth Casson... | add load/store FP indexed instructions to minor_31.csv
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2021-05-14 |
Luke Kenneth Casson... | add FP load test lfsx
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2021-05-14 |
Luke Kenneth Casson... | when setting x <- GPR(RA) make sure read_regs is added...
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2021-05-14 |
Luke Kenneth Casson... | add GPR-underscore read of regs
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2021-05-14 |
Luke Kenneth Casson... | add FRA ISACaller name decoding
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2021-05-14 |
Luke Kenneth Casson... | add FRA-FRT to power enums
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2021-05-14 |
Luke Kenneth Casson... | add first FP load test, still a lot TODO
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2021-05-14 |
Luke Kenneth Casson... | add FPR (FP Regfile) to ISACaller
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2021-05-14 |
Luke Kenneth Casson... | add in FPR.getz and support for FPR(x) in ISA parser
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2021-05-14 |
Luke Kenneth Casson... | add FRA-FRT fp reg names to ISACaller parser
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2021-05-14 |
Luke Kenneth Casson... | add fpmove.mdwn from v3.0B p150 book I section 4.6.5
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2021-05-14 |
Luke Kenneth Casson... | clarify, comments
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2021-05-14 |
Luke Kenneth Casson... | add FPADD, FPSUB, FPMUL, FPDIV quick hacked functions
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2021-05-14 |
Luke Kenneth Casson... | add very quick float convert to SelectableInt
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2021-05-14 |
Luke Kenneth Casson... | add import of DOUBLE/SINGLE to pywriter
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2021-05-14 |
Luke Kenneth Casson... | add SINGLE function to helpers, for FP Store
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2021-05-14 |
Luke Kenneth Casson... | add first pass at DOUBLE helper function for FP ISACaller...
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2021-05-14 |
Luke Kenneth Casson... | add zero-variant (RA|0) in fpload pseudocode, cleaner...
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2021-05-14 |
Luke Kenneth Casson... | add fpstore.mdwn
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2021-05-14 |
Luke Kenneth Casson... | add fpload.mdwn for FP simulation
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2021-05-11 |
Luke Kenneth Casson... | add setting of MSR "PR" bit for when running MMU test
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commit | commitdiff | tree |
2021-05-10 |
Luke Kenneth Casson... | extra checks on ldst exception unit test
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2021-05-10 |
Luke Kenneth Casson... | fix MemException, return correct address in DAR
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2021-05-10 |
Luke Kenneth Casson... | testing load misaligned
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2021-05-10 |
Luke Kenneth Casson... | test_maxint, add zero onto 0xffffffffffffff
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2021-05-10 |
Luke Kenneth Casson... | add first LD/ST exceptions test case for ISACaller
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2021-05-10 |
Luke Kenneth Casson... | save SVSRR0 in trap, if SVP64 mode enabled
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2021-05-10 |
Luke Kenneth Casson... | create new call_trap function in ISACaller
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2021-05-10 |
Luke Kenneth Casson... | add catch of MemException in ISACaller to raise unaligned...
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2021-05-10 |
Luke Kenneth Casson... | include Error keyword in message
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2021-05-10 |
Luke Kenneth Casson... | allow unaligned access exception to be raised in ISACaller...
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commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add ld/st misalignment test case
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commit | commitdiff | tree |
2021-05-06 |
Luke Kenneth Casson... | add relevant pred source/dest mask bits and create...
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2021-05-06 |
Luke Kenneth Casson... | add first SVP64 predicate dest-zeroing unit test
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2021-05-06 |
Luke Kenneth Casson... | remove non-predicated svp64 ISACaller tests
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2021-05-06 |
Luke Kenneth Casson... | improve format of docstrings for ISACaller SVP64 tests
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2021-05-06 |
Luke Kenneth Casson... | reformat SVP64 docstrings to vaguely resemble something...
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2021-05-06 |
Luke Kenneth Casson... | sphinx docstring highlight of SVP64 listings
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commit | commitdiff | tree |
2021-05-06 |
Luke Kenneth Casson... | move logical SVP64 test cases to separate file/directory
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2021-05-06 |
Luke Kenneth Casson... | whoops error in docstring
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commit | commitdiff | tree |
2021-05-06 |
Luke Kenneth Casson... | tidy up svp64 cases to make it better suited to documentation
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2021-05-05 |
Luke Kenneth Casson... | update about Copyright law when it comes to facts
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commit | commitdiff | tree |
2021-05-05 |
Luke Kenneth Casson... | add symlink to license
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2021-05-05 |
Luke Kenneth Casson... | add saturate SVP64 RM mode decode
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2021-05-05 |
Luke Kenneth Casson... | split PowerDecodeSubset do_copy into do_copy and do_get
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2021-05-05 |
Luke Kenneth Casson... | explicitly copy SV RM decoded fields in PowerDecodeSubset
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2021-05-05 |
Luke Kenneth Casson... | move SVP64 RM mode decoder into PowerDecodeSubset
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2021-05-05 |
Luke Kenneth Casson... | remove another verbose debug print
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2021-05-05 |
Luke Kenneth Casson... | add sv_input_record_layout to match SVP64RMModeDecode
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2021-05-04 |
Luke Kenneth Casson... | whoops must include SVSTATE in STATE regfile regspec...
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2021-05-04 |
Luke Kenneth Casson... | IssuerDecode2ToOperand needs svstate (matching msr...
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2021-05-04 |
Luke Kenneth Casson... | add more ALUHelper routines for fast3
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2021-05-04 |
Luke Kenneth Casson... | add ALUHelpers check_fast_spr3 for SVSRR0 checking
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2021-05-04 |
Luke Kenneth Casson... | add SVSRR0 to OP_RFID and OP_TRAP reg read/write
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