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Rework RAM port for nMigen compliance
2020-06-08 Jean THOMASRework RAM port for nMigen compliance
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2020-06-08 Jean THOMASRename LiteDRAM to gram
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2020-06-08 Jean THOMASConnect dramcore to SoC bus in ECPIX-5 example
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2020-06-08 Jean THOMASRename LiteDRAM to gram
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2020-06-08 Jean THOMASUse CSRPrefixProxy for exposing CSR
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2020-06-08 Jean THOMASAdd CSRPrefixProxy to gram.compat
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2020-06-08 Jean THOMASUpdate documentation
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2020-06-08 Jean THOMASAdd early code for libgram
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2020-06-08 Jean THOMASFix bugs in ECP5DDRPHY instanciation
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2020-06-08 Jean THOMASCleaning repo
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2020-06-08 Jean THOMASMigrate FIFO frontend from Migen to nMigen
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2020-06-08 Jean THOMASRework DFI interface code
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2020-06-08 Jean THOMASClean unused code
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2020-06-08 Jean THOMASAdd copyright
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2020-06-08 Jean THOMASRemove setaddr for submodule instanciation
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2020-06-08 Jean THOMASFix multiple drive issue
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2020-06-08 Jean THOMASAdd copyright
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2020-06-08 Jean THOMASFix PLL
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2020-06-05 Jean THOMASRemove bandwidth meter
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2020-06-05 Jean THOMASFix direction in stream assignment
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2020-06-05 Jean THOMASFix typo
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2020-06-05 Jean THOMASRemove useless variable
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2020-06-05 Jean THOMASFix signal drive error
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2020-06-05 Jean THOMASFix multi-driven signals in refresher
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2020-06-04 Jean THOMASBugfixing
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2020-06-04 Jean THOMASCorrect nMigen transition bugs
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2020-06-04 Jean THOMASAdd dram core as submodule
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2020-06-04 Jean THOMASMore nMigen conversion and fixes
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2020-06-04 Jean THOMASAdd second clock
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2020-06-04 Jean THOMASRemove diff pairs in ECPIX5Platform
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2020-06-03 Jean THOMASInitial commit
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