projects
/
yosys.git
/ search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Merge pull request #2436 from dalance/fix_generate
2021-01-28
Claire Xen
Merge pull request #2535 from Ravenslofty/scc-specify
commit
|
commitdiff
|
tree
2021-01-24
Claire Xen
Merge pull request #2558 from YosysHQ/dave/chandle-dpi
commit
|
commitdiff
|
tree
2021-01-20
Claire Xen
Merge pull request #2552 from YosysHQ/claire/yosyshq
commit
|
commitdiff
|
tree
2021-01-20
Claire Xenia Wolf
Switch verific bindings from Symbiotic EDA flavored...
Signed-off-by:
Claire Xen
ia Wolf <claire@clairexen.net>
commit
|
commitdiff
|
tree
2021-01-13
Claire Xen
Merge pull request #2537 from pepijndevos/spice
commit
|
commitdiff
|
tree
2020-12-27
Claire Xen
Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS...
commit
|
commitdiff
|
tree
2020-12-01
Claire Xen
Merge pull request #2463 from georgerennie/fix_verilog_front...
commit
|
commitdiff
|
tree
2020-11-25
Claire Xen
Merge pull request #2133 from dh73/nodev_head
commit
|
commitdiff
|
tree
2020-10-19
Claire Xenia Wolf
Fix argument handling in connect_rpc
Signed-off-by:
Claire Xen
ia Wolf <claire@symbioticeda.com>
commit
|
commitdiff
|
tree
2020-10-01
Claire Xenia Wolf
Ignore empty parameters in Verilog module instantiations
Signed-off-by:
Claire Xen
ia Wolf <claire@symbioticeda.com>
commit
|
commitdiff
|
tree