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intel_alm: cleanup duplication
2020-04-24
Dan Ravensloft
intel_alm: cleanup duplication
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2020-04-23
Dan Ravensloft
intel_alm: work around a Quartus ICE
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2020-04-21
Marcelina Kościelnicka
bugpoint: Don't remove modules or cells while iterating...
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2020-04-21
Dan Ravensloft
intel_alm: Documentation improvements
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2020-04-21
Marcelina Kościelnicka
write_json: dump default parameter values
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2020-04-21
Marcelina Kościelnicka
Use default parameter value in getParam
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2020-04-21
Marcelina Kościelnicka
hierarchy: Convert positional parameters to named.
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2020-04-21
Marcelina Kościelnicka
ilang, ast: Store parameter order and default value...
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2020-04-21
Marcelina Kościelnicka
idict: Make iterator go forward.
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2020-04-16
Marcelina Kościelnicka
opt_expr: Fix X and CO outputs for $alu identity-mapping...
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2020-04-15
Marcelina Kościelnicka
Fix the truth table for $_SR_* cells.
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2020-04-15
Marcelina Kościelnicka
Get rid of dffsr2dff.
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2020-04-15
Marcelina Kościelnicka
opt_clean: Add missing assignments to opt.did_something.
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2020-04-15
Dan Ravensloft
synth_intel_alm: VQM support
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2020-04-15
Marcelina Kościelnicka
setundef: Improve error messages.
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2020-04-15
Marcelina Kościelnicka
json: Update format documentation.
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2020-04-15
Dan Ravensloft
synth_intel_alm: alternative synthesis for Intel FPGAs
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2020-04-15
Marcelina Kościelnicka
abc9_ops: Add a check ensuring that connected port...
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2020-04-14
Marcelina Kościelnicka
opt_expr: Add more $alu optimizations.
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2020-04-14
Marcelina Kościelnicka
dffinit: Avoid setting init parameter to zero-length...
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2020-04-13
Marcelina Kościelnicka
opt_expr: Optimize multiplications with low 0 bits...
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2020-04-12
Xiretza
Add .gitignore to tests/select/
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2020-04-09
Marcelina Kościelnicka
[NFCI] Deduplicate builtin FF cell types list
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2020-04-08
Xiretza
Add constids.inc to final install
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2020-04-02
Marcin Kościelnicki
simcells.v: Generate the fine FF cell types by a python...
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2020-04-02
Marcin Kościelnicki
iopadmap: Fix z assignment to inout port
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2020-03-22
R. Ou
iopadmap: Attempt to give new wires/cells meaningful...
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2020-03-20
Marcin Kościelnicki
xilinx: Mark IOBUFDS.IOB as external pad
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2020-03-19
Marcin Kościelnicki
fsm_extract: Initialize celltypes with full design.
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2020-02-27
Piotr Binkowski
xilinx: mark IOBUFDSE3 IOB pin as external
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2020-02-15
Marcin Kościelnicki
tests/aiger: Add missing .gitignore
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2020-02-15
Tim 'mithro' Ansell
show: Add -nobg argument.
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07
Marcin Kościelnicki
xilinx: Initial support for LUT4 devices.
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2020-02-07
Marcin Kościelnicki
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for Spartan 3A DSP block RAMs.
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2020-02-06
Marcin Kościelnicki
edif: more resilience to mismatched port connection...
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2020-02-02
Marcin Kościelnicki
xilinx: use RAM32M/RAM64M for memories with two read...
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2020-02-01
Marcin Kościelnicki
json: remove the 32-bit parameter special case
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2020-01-29
Marcin Kościelnicki
xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-28
Pepijn de Vos
redirect fuser stderr to /dev/null
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