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shregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-04
Jim Lawson
Ensure fid() calls make_id() for consistency; tests...
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2019-02-26
Jim Lawson
Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-23
Jim Lawson
Address requested changes - don't require non-$ name.
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2019-02-19
Jim Lawson
Fix normal (non-array) hierarchy -auto-top.
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2019-02-15
Jim Lawson
Removed unused variables, functions.
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2019-02-15
Jim Lawson
Append (instead of over-writing) EXTRA_FLAGS
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2019-02-15
Jim Lawson
Define basic_cell_type() function and use it to derive...
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2019-02-15
Jim Lawson
Update cells supported for verilog to FIRRTL conversion.
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2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27
Jim Lawson
Remove unused functions.
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2018-08-27
Jim Lawson
Merge pull request #3 from YosysHQ/master
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2018-08-23
Jim Lawson
Add support for module instances.
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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