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Add test for random rlcd(l/r) instructions
2020-05-13
Michael Nolan
Add test for random rlcd(l/r) instructions
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2020-05-13
Michael Nolan
Fix bug in rotator preventing use of 64 bit rlcl/r
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2020-05-13
Michael Nolan
Update to latest wiki version
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2020-05-13
Michael Nolan
Fix too wide bitfield being selected for opcode 30
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2020-05-13
Michael Nolan
Fix weirdness with rldicl and friends in test_caller.py
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2020-05-13
Michael Nolan
Add support for OP_EXTS
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2020-05-13
Michael Nolan
Add missing input stage and pipe_data
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2020-05-13
Michael Nolan
Fix bug with ROTL32 helper
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2020-05-13
Michael Nolan
Somewhat working now?
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2020-05-13
Michael Nolan
Integrate rotator.py into shift_rot unit
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2020-05-13
Michael Nolan
Update cmp test in test_caller.py
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2020-05-13
Michael Nolan
Add assertions to ALU and shift_rot test that the instructio...
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2020-05-13
Michael Nolan
Add SHIFT_ROT FU
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2020-05-13
Michael Nolan
Modify alu test to put reg1 *OR* reg3 into alu input A
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2020-05-13
Michael Nolan
Update TODO
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2020-05-12
Michael Nolan
Add new shift_rot FU for shifts and rotates
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2020-05-12
Michael Nolan
Remove rotates and shifts from alu
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2020-05-11
Michael Nolan
Massively spead up test_pipe_caller.py
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2020-05-11
Michael Nolan
Revert "Greatly speed up test_pipe_caller.py"
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2020-05-11
Michael Nolan
Greatly speed up test_pipe_caller.py
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2020-05-11
Michael Nolan
Reverse bit order for cr0 in proof
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2020-05-11
Michael Nolan
Check output of cr0 from alu
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2020-05-11
Michael Nolan
Add carry in input to alu testbench
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2020-05-11
Michael Nolan
Add ability to specify initial state for SPRs
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2020-05-11
Michael Nolan
Fix proof_input_stage.py
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2020-05-11
Michael Nolan
Fix rlwimi by reordering the inputs *again*
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2020-05-11
Michael Nolan
Re-enable rlwinm test
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2020-05-11
Michael Nolan
Check write register number too
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2020-05-11
Michael Nolan
Reorder the register reads so the field in read_reg2...
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2020-05-11
Michael Nolan
Have test_pipe_caller actually read from the registers...
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2020-05-11
Michael Nolan
Actually implement rlwimi
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2020-05-10
Michael Nolan
Add test for rlwnm
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2020-05-10
Michael Nolan
Implement rlwimi as well
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2020-05-10
Michael Nolan
Implement rlwinm in alu
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2020-05-10
Michael Nolan
Add test for rlwinm
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2020-05-10
Michael Nolan
Reduce BMC depth on proof_main_stage.py
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2020-05-09
Michael Nolan
Add shift left and shift right to main stage proof
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2020-05-09
Michael Nolan
Handle algebraic shifts too
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2020-05-09
Michael Nolan
Implement logical shift right
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2020-05-09
Michael Nolan
Add support for sld
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2020-05-09
Michael Nolan
Change shift left to be implemented with rotate and...
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2020-05-09
Michael Nolan
Add mask generator for shift class instructions
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2020-05-09
Michael Nolan
Add shift left opcode to main_stage
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2020-05-09
Michael Nolan
Fix broken mask when x == y
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2020-05-09
Michael Nolan
Add right shift test to test_caller.py
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2020-05-09
Michael Nolan
Add shift test to test_caller, fix fixedshift being...
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2020-05-09
Michael Nolan
Fix helpers.py not playing nicely with selectableInts
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2020-05-09
Michael Nolan
Add reversed add and subtract, as well as lshift and...
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2020-05-09
Michael Nolan
Minor cleanup
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2020-05-08
Michael Nolan
Oops, forgot pipeline.py
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2020-05-08
Michael Nolan
Add tests for immediates, add subf to tests
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2020-05-08
Michael Nolan
Add comments about the purpose of each alu stage
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2020-05-08
Michael Nolan
Add test for alu against simulator
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2020-05-08
Michael Nolan
Add assertions for output stage cr0
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2020-05-08
Michael Nolan
Add output stage
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2020-05-08
Michael Nolan
Add and or and xor to main_stage
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2020-05-08
Michael Nolan
Add carry in and out
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2020-05-08
Michael Nolan
Have input_stage set the b operand to imm_data if it...
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2020-05-08
Michael Nolan
Add extra bits (carry, overflow, etc) to input and...
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2020-05-08
Michael Nolan
Begin adding main ALU stage
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2020-05-08
Michael Nolan
Convert alu to use the op in ctx
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2020-05-08
Michael Nolan
Add FPPipeContext to alu pipe_data
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2020-05-08
Michael Nolan
Add handling of A inversion and B input
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2020-05-08
Michael Nolan
Begin adding input stage of alu
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2020-05-08
Michael Nolan
Add pipe data for ALU pipeline
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2020-05-08
Michael Nolan
Update gitignore in isa dir
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2020-05-08
Michael Nolan
Separate out ALU Input record from alu_hier.py
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2020-05-07
Michael Nolan
Add test_branch_loop_ctr
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2020-05-07
Michael Nolan
Add tests for conditional branches
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2020-05-07
Michael Nolan
Ooops, forgot comparefixed.patch
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2020-05-07
Michael Nolan
Get test_cmp working
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2020-05-07
Michael Nolan
Fix test_mtcrf. Test has been verified against qemu
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2020-05-07
Michael Nolan
Make FieldSelectableInt accept slices for set and get
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2020-05-07
Michael Nolan
Add handling of add with comparison
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2020-05-07
Michael Nolan
Fix bug with comparisons in selectable_int.py
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2020-05-07
Michael Nolan
Add test_mfcr
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2020-05-06
Michael Nolan
Re-enable test_mtcrf
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2020-05-06
Michael Nolan
Add length helper for getting length of a selectable int
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2020-05-06
Michael Nolan
Add helper functions to replace direct comparison in...
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2020-05-06
Michael Nolan
Look up spr length from spr table
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2020-05-06
Michael Nolan
Add dict of spr properties to power_enums
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2020-05-06
Michael Nolan
Implement bctr and mtspr
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2020-05-06
Michael Nolan
Properly implement LR and CTR
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2020-05-06
Michael Nolan
Add ability to patch generated isa files
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2020-05-06
Michael Nolan
Sorta kinda working bl and blr - need to properly implement lr
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2020-05-05
Michael Nolan
Add rudimentary branch capability
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2020-05-05
Michael Nolan
Fix broken test_decoder_gas
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2020-05-02
Michael Nolan
Read decoder tables from wiki submodule instead of web
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2020-04-10
Michael Nolan
Update libreriscv to fix test_mtcrf
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2020-04-06
Michael Nolan
Convert instruction info from tuple to namedtuple
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2020-04-06
Michael Nolan
Add test for addpcis
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2020-04-06
Michael Nolan
Begin adding PC to caller.py
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2020-04-06
Michael Nolan
Fix broken tests from parser update
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2020-04-06
Michael Nolan
Auto insert instruction fields into the namespace
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2020-04-05
Michael Nolan
Autogenerate all.py
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2020-04-05
Michael Nolan
Handle new changes in pseudocode parser
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2020-04-05
Michael Nolan
Handle opcodes returning EXTS() results
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2020-04-05
Michael Nolan
Fix bug 281
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2020-04-05
Michael Nolan
Add in _reg and immediate support
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2020-04-05
Michael Nolan
Fix issue with memory load/store byte order
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