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dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs
2019-09-06
Giacomo Travaglini
dev-arm: Add GICv3 unimplemented Hyp Active Priorities...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Allow 32-bit access to GITS_TYPER
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Cpu interface groupEnabled check for global...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Check if INTID group is enabled when reading...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Writing GICD_CTLR should trigger an update
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Rewrite GICv3 update
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Fix GICv3 IGRPMOD writes
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: SGI registers undecoded in AArch32
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Fix SGI generation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-05
Giacomo Travaglini
dev-arm: Improper translation slot release in SMMUv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-30
Giacomo Travaglini
arm,kvm: Fix python imports from global namespace
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-26
Giacomo Travaglini
dev-arm: Fix GICv3 ITS indexing error
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-26
Giacomo Travaglini
dev-arm: Fix GITS_BASER initialization/access
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-22
Giacomo Travaglini
dev-arm: Start using GITS_CTLR.quiescent bit
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-22
Giacomo Travaglini
dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
dev-arm: Add redistributor-stride property to GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Replace occ of opModeToEL(currOpMode/cpsr...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Replace direct use cpsr.el with currEL helper
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Overload currEL helper with CPSR argument
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Rewrite the currEL helper method to use opModeToEL
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
dev-arm: Add GITS_PIDR2 register to the ITS memory map
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRx
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-12
Giacomo Travaglini
dev-arm: Enable DTB autogeneration in GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-12
Giacomo Travaglini
dev-arm: Fix PCI node's interrupt-map property
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-12
Giacomo Travaglini
dev-arm: Use FdtState to generate GIC properites
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-12
Giacomo Travaglini
python: FdtState using interrupt-cells
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2019-08-07
Giacomo Travaglini
dev-arm: Perform SMMUv3 CFG Invalidation at device...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-05
Giacomo Travaglini
arch-arm: Implement ARMv8.1-PAN, Privileged access...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-05
Giacomo Travaglini
arch-arm: Rewrite MSR immediate instruction class
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-30
Giacomo Travaglini
dev-arm: Rewrite SMMUv3 Commands
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: Fix SMMUv3 CMDQ wrapping
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: Polish SMMUv3 CMDQ setup
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: Define enum masks for SMMU_CR0 register
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: SMMUv3 Table walks using TnSZ
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-25
Giacomo Travaglini
dev-arm: Use override keyword for SMMUv3 PTOPS
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-19
Giacomo Travaglini
arch-arm: Implement ARMv8.1-HPD, Hierarchical permission...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-19
Giacomo Travaglini
arch-arm: Add HPD bit for TCR_EL2/EL3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-19
Giacomo Travaglini
arch-arm: Clean Fault generation when processing Long...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-17
Giacomo Travaglini
arch-arm: Use ExceptionLevel type in TlbEntry
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-16
Giacomo Travaglini
dev-arm: Fix SMMUv3 ContextDescriptor pointer shift
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-16
Giacomo Travaglini
cpu: isDrained renamed to isCpuDrained
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-07-01
Giacomo Travaglini
dev-arm: Use global import path for MemObject
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-26
Giacomo Travaglini
dev-arm: Remove un-needed Q_CONS_PROD_MASK macro
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-20
Giacomo Travaglini
configs: Fix NULL dram-lowp regressions
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-17
Giacomo Travaglini
arch-arm: Move the memacc_code before op_wb in fp loads
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-17
Giacomo Travaglini
dev-arm: Reapply GICv3 changes that were lost during...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-09
Giacomo Travaglini
base: Provide a getter for Fiber::started boolean variable
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-09
Giacomo Travaglini
base: Rename TestFiber into SwitchingFiber
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-06-07
Giacomo Travaglini
arch-arm: Fix WalkerState,Descriptors default constructor
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-24
Giacomo Travaglini
arch-arm: Fix fallthrough when trapping at EL2
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-23
Giacomo Travaglini
arch-arm: Trap virtual accesses to GICv3 SGI registers
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-23
Giacomo Travaglini
arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-23
Giacomo Travaglini
arch-arm: Change mcrMrc15TrapToHyp signature
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-22
Giacomo Travaglini
dev-arm: Provide a GICv3 ITS Implementation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-14
Giacomo Travaglini
Revert "cpu: fix how a thread starts up in MinorCPU"
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-14
Giacomo Travaglini
Revert "cpu: stop scheduling suspended threads in MinorCPU"
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-14
Giacomo Travaglini
Revert "cpu: fix branching when thread is suspended...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-03
Giacomo Travaglini
dev: StreamID generation in DMA device
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Store a PhysProxy port in Gicv3Redist
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Add named variable for GICD_TYPER.IDBits
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Read correct version of ICC_BPR register
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Get a Gicv3Redistributor ptr from phys address
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Add several LPI methods in Gicv3Redistributor
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Take LPIs into account when interacting with...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Fix GICv3 LPIs priority value
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Disable LPI Configuration Table caching
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Check EnableLPIs before checking for pending...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: GICv3 LPI tables are using physical addresses
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Fix GICv3 LPI loop
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-05-02
Giacomo Travaglini
dev-arm: Fix Bitwise operation in GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-29
Giacomo Travaglini
arch-arm: Faults DebugFlag now printing inst opcode...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-29
Giacomo Travaglini
arch-arm: Report real instruction encoding when Undefined
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-26
Giacomo Travaglini
arch-arm: updateMiscReg not setting isHyp in aarch64
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
arch-arm: Remove un-needed hyp flag in TLBI operations
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
arch-arm: Correct target EL field in TLBI operations
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
dev-arm: Move GICv3 (Re)Ditributor address in Realview.py
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
dev-arm: Limit number of max PE in GICv3 to 128
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
dev-arm: Add GICv4 extension switch in GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-25
Giacomo Travaglini
dev-arm: Check for maximum number of supported PE in...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-11
Giacomo Travaglini
arch-arm: Enable PMSELR_EL0 read in PMU
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-10
Giacomo Travaglini
cpu: O3 switchFreeList checking VecElems instead of...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-04-02
Giacomo Travaglini
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-28
Giacomo Travaglini
arch-arm: Fix index generation for VecElem operands
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-27
Giacomo Travaglini
dev-arm: Rename GIC maintenance interrupt from ppint...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-27
Giacomo Travaglini
dev-arm: Fix GICv3 overflow for INTID > 256
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-27
Giacomo Travaglini
dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-26
Giacomo Travaglini
dev-arm: Set/Unset dma coherent mode from python
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-22
Giacomo Travaglini
base: Fix CircularQueue's operator-= when negative...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-22
Giacomo Travaglini
base: Fix CircularQueue when diffing iterators
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-01
Giacomo Travaglini
dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-03-01
Giacomo Travaglini
dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-18
Giacomo Travaglini
arch-arm: Move GICv3 detection at startup time
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-18
Giacomo Travaglini
base: Fix enums checkpointing
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-15
Giacomo Travaglini
cpu: Fix fast build broken due to unused variable
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-13
Giacomo Travaglini
configs: simpoint-profile usable with NonCachingCPUs...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-08
Giacomo Travaglini
arch-arm: Fix Virtual interrupts in AArch64
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-08
Giacomo Travaglini
arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-02-08
Giacomo Travaglini
arch-arm: Allow ArmPPI usage for PMU
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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