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Disable Assert statements until they are natively supported in nMigen
2020-07-09 Jean THOMASDisable Assert statements until they are natively supported...
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2020-07-09 Jean THOMASComment buggy assertions
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2020-07-09 Jean THOMASAdd imports for Assert & Assume in FakePHY
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2020-07-09 Jean THOMASFix counter reset condition bug
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2020-07-09 Jean THOMASFix syntax in FakePHY assertions
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2020-07-09 Jean THOMASUse assertions as a temporary replacement for Display...
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2020-07-09 Jean THOMASRemove unused BitFlip
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2020-07-09 Jean THOMASUpdate build script to include software version
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2020-07-08 Jean THOMASAdd temporary code for SoC tests with FakePHY
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2020-07-08 Jean THOMASPort FakePHY to nMigen
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2020-07-08 Jean THOMASMatch ECPIX-5 DRAM parameters in Micron's model
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2020-07-08 Jean THOMASImport fake PHY from LiteDRAM (non functionnal ATM)
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2020-07-08 Jean THOMASFix styling
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2020-07-08 Jean THOMASAdd test case for AntiStarvation
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2020-07-08 Jean THOMASFix bugs in _AntiStarvation
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2020-07-08 Jean THOMASUpdate memtest code
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2020-07-08 Jean THOMASRemove useless variables in _Steerer, ensure command...
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2020-07-08 Jean THOMASMake an Elaboratable out of the anti_starvation function
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2020-07-08 Jean THOMASAdd links to various docs that have been helpful
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2020-07-08 Jean THOMASDrop YoWASP, build Yosys and SymbiYosys from source
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2020-07-08 Jean THOMASFix dram_model path in .gitattributes
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2020-07-08 Jean THOMASFix clock input
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2020-07-08 Jean THOMAScke => clk_en in SoC testbench
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2020-07-07 Jean THOMASUpdate cke => clk_en in test
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2020-07-07 Jean THOMASFix code styling
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2020-07-07 Jean THOMASFix code styling
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2020-07-07 Jean THOMASReplace cke with clk_en
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2020-07-07 Jean THOMASFix CRG PLL parameters (fixing #23)
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2020-07-06 Jean THOMASRename from cke to clk_en
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2020-07-06 Jean THOMASMake RefreshTimer fully synchronous (#24)
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2020-07-06 Jean THOMASAdd write transactions in the simulation testbench
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2020-07-06 Jean THOMASReduce amount of combinatorial statements to improve...
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2020-07-06 Jean THOMASFix formal support in FHDLTestCase
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2020-07-03 Jean THOMASRemove Diamond install script
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2020-07-03 Jean THOMASAdd SourceHut badge
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2020-07-03 Jean THOMASAdd .gitattributes file
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2020-07-03 Jean THOMASRemove Diamond install as it only comes with models...
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2020-07-03 Jean THOMASUse CRG parameters that actually work on hardware
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2020-07-03 Jean THOMASUpdate CRG with parameters that work IRL
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2020-07-03 Jean THOMASInvert condition in runsimcrg.sh
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2020-07-03 Jean THOMASRemove remainings from TRELLIS_IO
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2020-07-03 Jean THOMASCheck if YOSYS env var is set and use it as YOSYS executable
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2020-07-03 Jean THOMASUse Yosys from YoWASP
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2020-07-03 Jean THOMASFix permissions for simulation script
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2020-07-03 Jean THOMASAdd simulation script into SourceHut builds
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2020-07-03 Jean THOMASExclude DDRDLLA from tree
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2020-07-03 Jean THOMASEnsure dramsync runs at 100Mhz, sync2x at 200Mhz
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2020-07-03 Jean THOMASRemove DDRDLLA
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2020-07-03 Jean THOMASAdd build script for SourceHut
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2020-07-03 Jean THOMASAdd tests in DFI Injector for odt and reset signals
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2020-07-03 Jean THOMASCheck for additional signals in phase injector at t=0
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2020-07-03 Jean THOMASAdd DFI injector test case
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2020-07-03 Jean THOMASUpdate simulation gitignore
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2020-07-03 Jean THOMASUpdate gram simulation documentation
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2020-07-03 Jean THOMASAdd cleaning pass
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2020-07-03 Jean THOMASFix autopep8 madness
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2020-07-03 Jean THOMASRework CRG simulation
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2020-07-03 Jean THOMASExternalize CRG into its own file
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2020-07-03 Jean THOMASAdd devel doc
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2020-07-03 Jean THOMASAdd test for Refresher
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2020-07-03 Jean THOMASRefactor generic_test execution
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2020-07-03 Jean THOMASUse spaces for indentation
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2020-07-03 Jean THOMASAdd tests for core/refresher.py
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2020-07-03 Jean THOMASRemoving reset=0 attribute as it is already the default...
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2020-07-02 Jean THOMASUse reset signal from dramsync instead of sync
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2020-07-02 Jean THOMASMake RefreshPostponer more similar to LiteDRAM's
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2020-07-02 Jean THOMASFix RefreshPostponer output stuck to 1
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2020-07-02 Jean THOMASFlatten specific parts of the designs
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2020-07-02 Jean THOMASAdd missing command issue strobe for ZQ calibration
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2020-07-02 Jean THOMASRemove PyYAML dependency
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2020-07-02 Jean THOMASFix register addresses, add missing command_issue strobe
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2020-07-02 Jean THOMASSet names to prevent CSR/DomainRenamer incompatibility
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2020-07-02 Jean THOMASAdd DDRDLLA patch
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2020-07-01 Jean THOMASFix merge
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2020-07-01 Jean THOMASRework indentation and add Wishbone tests
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2020-07-01 Jean THOMASAdd Wishbone interaction code
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2020-07-01 Jean THOMASAdd Wishbone interaction code
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2020-07-01 Jean THOMASFix Iverilog simulation
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2020-07-01 Jean THOMASGenerate ilang file
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2020-06-30 Jean THOMASBuild nMigen gateware in a specific folder
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2020-06-30 Jean THOMASRemove LED code in CRG
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2020-06-30 Jean THOMASRemove Minerva dependency
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2020-06-30 Jean THOMASApplying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
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2020-06-29 Jean THOMASDefine simulation time as a parameter
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2020-06-29 Jean THOMASDefine PLL's PHASELOADREG input
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2020-06-29 Jean THOMASUse -n option in vvp to enable CTRL+C
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2020-06-29 Jean THOMASFix PLL instanciation code for CRG simulation
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2020-06-29 Jean THOMASDump whole module
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2020-06-29 Jean THOMASFix DQSBUFM floating DYNDELAY
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2020-06-29 Jean THOMASSet DRAM's CK_N to low
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2020-06-29 Jean THOMASFix autopep8 madness
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2020-06-29 Jean THOMASUse BB instead of TRELLIS_IO
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2020-06-29 Jean THOMASFix CRG, revert to resetful sync domain
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2020-06-29 Jean THOMASSet UART RX to 1'b1
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2020-06-29 Jean THOMASAdd -Wall to simulations
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2020-06-26 Jean THOMASAdd testbench for SoC simulation
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2020-06-26 Jean THOMASUse FST instead of VCD
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2020-06-26 Jean THOMASExclude .fst files
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2020-06-26 Jean THOMASAdd DDRSoC simulation
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2020-06-26 Jean THOMASAdd gitignore for simulation folder
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