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arch-arm: Report real instruction encoding when Undefined
2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Move GICv3 (Re)Ditributor address in Realview.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Limit number of max PE in GICv3 to 128
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Add GICv4 extension switch in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-25 Giacomo Travaglinidev-arm: Check for maximum number of supported PE in...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-10 Giacomo Travaglinicpu: O3 switchFreeList checking VecElems instead of...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-28 Javier Setoainarch-arm: Fix use of bitwise operators on booleans
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-28 Giacomo Travagliniarch-arm: Fix index generation for VecElem operands
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Rename GIC maintenance interrupt from ppint...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Fix GICv3 overflow for INTID > 256
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-27 Giacomo Travaglinidev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-26 Giacomo Travaglinidev-arm: Set/Unset dma coherent mode from python
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-25 Javier Setoainarch-arm: Add missing fall-through defaults
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-22 Tiago Mucksim-se: Fixed initialization array size
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2019-03-22 Giacomo Travaglinibase: Fix CircularQueue's operator-= when negative...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-22 Giacomo Travaglinibase: Fix CircularQueue when diffing iterators
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-01 Giacomo Travaglinidev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-01 Giacomo Travaglinidev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-19 Giacomo Gabriellicpu: Add ISA* getter in Thread interface
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2019-02-18 Giacomo Travagliniarch-arm: Move GICv3 detection at startup time
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-18 Giacomo Travaglinibase: Fix enums checkpointing
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-15 Giacomo Travaglinicpu: Fix fast build broken due to unused variable
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-13 Giacomo Travagliniconfigs: simpoint-profile usable with NonCachingCPUs...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-08 Ruben Ayrapetyanarch-arm: Fix initialization of PMU counters
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2019-02-07 Giacomo Travagliniconfigs, arch-arm: Using AddrRange for Realview mem_regions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-07 Giacomo Travagliniconfigs: Unifiy interpretation of Realview mem_regions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-02-01 Anouk Van Laerdev, arm: Removed contextId variable
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniconfigs: Enable DTB autogeneration in starter_fs.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autogeneration
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instruction
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2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-25 Nicholas Lindsaypython: Always throw TypeError on slave-slave connections
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2019-01-24 Rekai Gonzalez-Alber... cpu-o3: O3 LSQ Generalisation
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2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-22 Sascha Bischoffmem: Add tryTiming suppport to CommMonitor
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2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a VExpress_GEM5_V2 platform with GICv3...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Jairo Balartdev-arm: Add a GICv3 model
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 Giacomo Travaglinibase: Make it possible to convert strings to enums
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Jan-Peter Larssondev, arm: Warn on PL011 DMA disable
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added VGIC GICV_IIDR response
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Implement GIC-400 model from GicV2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Giacomo Travaglinidev-arm: Move VGic from Realview.py to Gic.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-04 Anouk Van Laerdev-arm: Added unimplemented GICv2 GICC_DIR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-03 Curtis Dunhamarm: properly handle RES0/1 for SCTLRs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-19 Giacomo Travagliniarch-arm: Add Crypto in SE mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-08 Giacomo Travaglinibase, systemc: Fix clang compilation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-07 Giacomo Travaglinimem: Compile tracePacket only when TRACING_ON is defined
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Matteo Andreozziext: Remove unused bankwiseMode variable
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2018-12-06 Rekai Gonzalez-Alber... base: Ported circlebuf to CircularQueue
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Rekai Gonzalez-Alber... base: Iterable CircularQueue implementation
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2018-12-06 Giacomo Travagliniext: Build googlemock with googletest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Import googlemock, release version 1.8.0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-03 Giacomo Gabriellibase: Add type alias for raw pointer in RefCountingPtr
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2018-11-28 Matteo Andreozziarch-arm: clang compilation fixes
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-28 Giacomo Travaglinitests: Convert IniFile unit test to a GTest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-16 Matteo Andreozzimem: avoid calling regStat twice on a QoSPolicy
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move BitUnion overloading to show/parseParams
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move paramIn/Out definition to header file
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-12 Giacomo Travaglinisystemc: Push python headers on top of sources
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Don't panic when EOIR a non active PPI
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Fix Gicv2 distributor group register
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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