2019-09-30 | Benjamin Herrenschmidt | Update dependency ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Add distclean to Makefile ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | New C based JTAG debug tool ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Add core debug module ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org |
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2019-09-20 | Benjamin Herrenschmidt | Add jtag support in simulation via a socket ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Add DMI address decoder ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Wishbone debug module ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Add a debug (DMI) bus and a JTAG interface to it on... ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-20 | Benjamin Herrenschmidt | Use a 3 way WB arbiter and cleanup fpga toplevel ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Switch soc to use std_ulogic ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Share soc.vhdl between FPGA and sim ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Pass wishbone record to bram memory module ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Rework wishbone slave address decoding ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Move wishbone arbiter out of the core ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Re-indent and reformat soc.vhdl ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-10 | Benjamin Herrenschmidt | Split FPGA toplevel from soc ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-09 | Benjamin Herrenschmidt | decode1 array fix header ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-09 | Benjamin Herrenschmidt | Use simulated UART in core test bench ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-09 | Benjamin Herrenschmidt | Make sim poll non-blocking ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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2019-09-09 | Benjamin Herrenschmidt | Add simulated UART design ...by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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