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stats: Update stats for monitor, cache and bus changes
2013-06-27 Andreas Hanssonstats: Update stats for monitor, cache and bus changes
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2013-06-27 Andreas Hanssonmem: Remove the cache builder
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2013-06-27 Andreas Hanssonconfig: Remove Clock parameter multiplication
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2013-06-27 Andreas Hanssonconfig: Add a BaseSESystem builder for re-use in regressions
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2013-06-27 Andreas Hanssontests: Prune 00.gzip from the regressions
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2013-06-27 Andreas Hanssonmem: Tidy up the bridge with const and additional checks
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2013-06-27 Andreas Hanssonmem: Fix CommMonitor style and response check
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2013-06-27 Andreas Hanssonmem: Align cache timing to clock edges
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2013-06-27 Andreas Hanssoncpu: Consider instructions waiting for FU completion...
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2013-06-27 Andreas Hanssonmem: Cycles converted to Ticks in atomic cache accesses
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2013-06-27 Andreas Hanssonscons: Identify runs that fail and runs with stats...
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2013-06-27 Andreas Hanssonbase: Fix address range granularity calculation
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2013-06-27 Andreas Hanssonmem: Remove a redundant heap allocation for a snoop...
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2013-06-27 Andreas Hanssonmem: Remove CoherentBus snoop port unused private member
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2013-06-24 Andreas Hanssonstats: Bump x86 stats
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2013-05-30 Andreas Hanssonstats: Update the stats to reflect bus and memory changes
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2013-05-30 Andreas Hanssonmem: More descriptive DRAM config names
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2013-05-30 Andreas Hanssonmem: Add bytes per activate DRAM controller stat
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2013-05-30 Andreas Hanssonmem: Add static latency to the DRAM controller
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2013-05-30 Andreas Hanssonmem: Spring cleaning of MSHR and MSHRQueue
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2013-05-30 Andreas Hanssonmem: Fix MSHR print format
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2013-05-30 Andreas Hanssoncpu: Prune the stale TraceCPU
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2013-05-30 Andreas Hanssoncpu: Add request elasticity to the traffic generator
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2013-05-30 Andreas Hanssoncpu: Block traffic generator when requests have to...
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2013-05-30 Andreas Hanssoncpu: Move traffic generator sending out of generator...
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2013-05-30 Andreas Hanssoncpu: Fold together the StateGraph and the TrafficGen
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2013-05-30 Andreas Hanssonmem: Make returning snoop responses occupy response...
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2013-05-30 Andreas Hanssonmem: Make the buses multi layered
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2013-05-30 Andreas Hanssonmem: Separate the two snoop response cases in the bus
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2013-05-30 Andreas Hanssonmem: Tidy up a few variables in the bus
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2013-05-30 Andreas Hanssonmem: Use unordered set in bus request tracking
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2013-05-30 Andreas Hanssonmem: Check for waiting state in bus draining
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2013-05-30 Andreas Hanssonmem: Add a LPDDR3-1600 configuration
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2013-05-30 Andreas Hanssonmem: Adapt the LPDDR2 to match a single x32 channel
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2013-05-30 Andreas Hanssonmem: Avoid explicitly zeroing the memory backing store
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2013-05-30 Andreas Hanssonutil: Auto generate the packet proto definitions
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2013-05-30 Andreas Hanssonbase: Avoid size limitation on protobuf coded streams
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2013-05-30 Andreas Hanssoncpu: Make hash struct instead of class to please clang
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2013-04-28 Andreas Hanssonconfig: Added memory type to t1000 regression
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2013-04-23 Andreas Hanssoncpu: Fix TraceGen flag initalisation
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2013-04-22 Andreas Hanssonmem: Address mapping with fine-grained channel interleaving
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2013-04-22 Andreas Hanssonmem: More descriptive enum names for address mapping
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2013-04-22 Andreas Hanssoncpu: Use request flags in trace playback
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2013-04-22 Andreas Hanssoncpu: Make the generators usable outside the TrafficGen...
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2013-04-22 Andreas Hanssonconfig: Add a mem-type config option to se/fs scripts
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2013-04-22 Andreas Hanssonmem: Add a WideIO DRAM configuration
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2013-04-22 Andreas Hanssonmem: Replace check with panic where inhibited should...
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2013-04-19 Andreas Hanssonstats: Update stats for ldr_ret_uop (changeset 35198406dd72)
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2013-04-17 Andreas Hanssondev: Fix a bug in the use of seekp/seekg
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2013-04-16 Andreas Hanssonstats: Bump the vortex stats to match latest behaviour
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2013-03-26 Andreas Hanssonutil: Add a utility script for decoding packet traces
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2013-03-26 Andreas Hanssonutil: Add a utility script for encoding packet traces
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2013-03-26 Andreas Hanssonstats: Update stats for cache retry event check
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2013-03-26 Andreas Hanssonstats: Update stats to reflect bus retry changes
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2013-03-26 Andreas Hanssonmem: Separate waiting for the bus and waiting for a...
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2013-03-26 Andreas Hanssonmem: Introduce a variable for the retrying port
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2013-03-26 Andreas Hanssonmem: Add a generic id field to the packet trace
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2013-03-26 Andreas Hanssonmem: Add optional request flags to the packet trace
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2013-03-26 Andreas Hanssoncpu: Remove CpuPort and use MasterPort in the CPU classes
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2013-03-20 Andreas Hanssoncpu: Avoid including inorder TLBUnit to avoid gcc LTO bug
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2013-03-18 Andreas Hanssonmem: Fix missing delete of packet in DRAM access
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2013-03-07 Andreas Hanssonbase: Fix address range granularity calculations
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2013-03-07 Andreas Hanssonruby: Fix gcc 4.8 maybe-uninitialized compilation error
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2013-03-07 Andreas Hanssonx86: Make the table walker reset the packet delay
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2013-03-01 Andreas Hanssonmem: Add check if SimpleDRAM nextReqEvent is scheduled
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2013-03-01 Andreas Hanssonmem: Add a method to build multi-channel DRAM configurations
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2013-03-01 Andreas Hanssonstats: Update stats to reflect SimpleDRAM changes
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2013-03-01 Andreas Hanssonmem: SimpleDRAM variable naming and whitespace fixes
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2013-03-01 Andreas Hanssonmem: Add support for multi-channel DRAM configurations
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2013-03-01 Andreas Hanssonmem: Merge interleaved ranges when creating backing...
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2013-03-01 Andreas Hanssonmem: Merge ranges in bus before passing them on
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2013-02-19 Andreas Hanssonmem: Fix sender state bug and delay popping
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2013-02-19 Andreas Hanssonscons: Fix warnings issued by clang 3.2svn (XCode 4.6)
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2013-02-19 Andreas Hanssonscons: Unify the flags shared by gcc and clang
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2013-02-19 Andreas Hanssonscons: Add warning delete with non-virtual destructor
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2013-02-19 Andreas Hanssonscons: Add warning for missing declarations
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2013-02-19 Andreas Hanssonscons: Add warning for overloaded virtual functions
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2013-02-19 Andreas Hanssonscons: Add warning for overloaded virtual functions
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2013-02-19 Andreas Hanssonscons: Add warning for missing field initializers
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2013-02-19 Andreas Hanssonscons: Fix up numerous warnings about name shadowing
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2013-02-19 Andreas Hanssonmem: Enforce strict use of busFirst- and busLastWordTime
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2013-02-19 Andreas Hanssonmem: Change accessor function names to match the port...
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2013-02-19 Andreas Hanssonmem: Make packet bus-related time accounting relative
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2013-02-19 Andreas Hanssonmem: Add deferred packet class to prefetcher
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2013-02-19 Andreas Hanssonsim: Make clock private and access using clockPeriod()
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2013-02-19 Andreas Hanssonx86: Move APIC clock divider to Python
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2013-02-19 Andreas Hanssonmem: Add predecessor to SenderState base class
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2013-02-19 Andreas Hanssonbase: Fix a bug in the address interleaving
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2013-02-19 Andreas Hanssonmem: Ensure trace captures packet fields before forwarding
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2013-02-15 Andreas Hanssonmem: Tighten up cache constness and scoping
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2013-02-14 Andreas HanssonRuby: Fix compilation errors on gcc 4.7 and clang 3.2
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2013-01-31 Andreas Hanssonmem: Add comments for the DRAM address decoding
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2013-01-31 Andreas Hanssonstats: Update stats for regressions using SimpleDDR3
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2013-01-31 Andreas Hanssonmem: Add DDR3 and LPDDR2 DRAM controller configurations
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2013-01-31 Andreas Hanssonmem: Separate out the different cases for DRAM bus...
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2013-01-28 Andreas Hanssonstats: Fix naming (BPredUnit to branchPred) for 20...
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2013-01-21 Andreas Hanssonscons: Disable protobuf if pkg-config and CheckLib...
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2013-01-14 Andreas Hanssonscons: Address clang 3.2 compilation error
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2013-01-14 Andreas Hanssonstats: Bump failing x86 regression stats
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2013-01-07 Andreas Hanssondev: Do not serialize timer parameters
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