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iris: Prepare resources before stencil blit operation
2019-10-29 Sagar Ghugeiris: Prepare resources before stencil blit operation
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Prepare depth resource if clear_depth enable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Prepare stencil resource before clear depth stencil
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeiris: Resolve stencil buffer lossless compression with...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Set stencil resolve enable bit
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel: Track stencil aux usage on Gen12+
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Add helper function for stencil buffer...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugeintel/blorp: Assign correct view while clearing depth...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Sagar Ghugegenxml/gen12: Add Stencil Buffer Resolve Enable bit
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-29 Nanley Cheryiris: Allocate main and aux surfaces together
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2019-10-29 Nanley Cheryiris: Determine aux offsets within configure_aux
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2019-10-29 Nanley Cheryiris: Bail resource creation upon aux creation error
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2019-10-29 Nanley Cheryiris: Drop iris_resource::aux::extra_aux::bo
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2019-10-28 Sagar Ghugeiris: Create resource with aux_usage MCS_CCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/isl: Support lossless compression with multisamples
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Get correct resource aux usage for copy
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/blorp: Use isl_aux_usage_has_mcs instead of comparing
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Define MCS_CCS state transitions and usages
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeiris: Initialize CCS to fast clear while using with MCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-28 Sagar Ghugeintel/isl: Don't reconfigure aux surfaces for MCS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Refactor disassembly of sources in...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Don't move immediate in register
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Set bits according to source file
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-22 Sagar Ghugeintel/compiler: Add Immediate support for 3 source...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugeintel: Add missing entry for brw_nir_lower_alpha_to_coverage...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugeintel/compiler: Remove emit_alpha_to_coverage workaround...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-10-21 Sagar Ghugenir: Add alpha_to_coverage lowering pass
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugeiris: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugegallium: Add PIPE_CAP_TEXTURE_SHADOW_LOD
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Sagar Ghugei965: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-30 Paulo Zanoniglsl: Add builtin functions for EXT_texture_shadow_lod
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2019-07-30 Paulo Zanoniglsl: Allow _textureCubeArrayShadow function to accept...
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2019-07-30 Paulo Zanonimesa: extension boilerplate for EXT_texture_shadow_lod
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2019-07-26 Sagar Ghugenir: Optimize umod lowering
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-24 Sagar Ghugenir: Add lowering for nir_op_irem and nir_op_imod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-23 Sagar Ghugeanv: Implement VK_KHR_imageless_framebuffer
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/tools: Add assembler unit tests for ROL/ROR instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/tools: Add ROL/ROR support in assembler
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add lower_rotate flag and set to true in all drivers
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/compiler: Emit ROR and ROL instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add optimization to use ROR/ROL instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugenir: Add urol and uror opcodes
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-07-01 Sagar Ghugeintel/compiler: Enable the emission of ROR/ROL instructions
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-06-25 Sagar Ghugeglsl: Fix round64 conversion function
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-06-04 Sagar Ghugeintel/compiler: Fix assertions in brw_alu3
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-04-12 Sagar Ghugeintel/fs: Remove unused condition from opt_algebraic...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-08 Sagar Ghugeiris: Track last VS URB entry size
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-08 Sagar Ghugeiris: Refactor code to share 3DSTATE_URB_* packet
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugespirv: Allow [i/u]mulExtended to use new nir opcode
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugenir/algebraic: Optimize low 32 bit extraction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugeglsl: [u/i]mulExtended optimization for GLSL
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2019-03-04 Sagar Ghugenir/glsl: Add another way of doing lower_imul64 for...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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2018-12-18 Sagar Ghugenir: Add a new lowering option to lower 3D surfaces...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
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