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Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-24 Dan Ravensloftintel_alm: cleanup duplication
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2020-04-23 Dan Ravensloftintel_alm: work around a Quartus ICE
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2020-04-21 Dan Ravensloftintel_alm: Documentation improvements
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2020-04-15 Dan Ravensloftsynth_intel_alm: VQM support
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2020-04-15 Dan Ravensloftsynth_intel_alm: alternative synthesis for Intel FPGAs
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2020-02-28 Dan RavensloftAdd -flowmap to synth and synth_ice40
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2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx
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2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp
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2019-07-24 Dan Ravensloftintel: Make -noiopads the default
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2019-07-23 Dan Ravensloftintel: Map M9K BRAM only on families that have it
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2019-07-18 Dan Ravensloftsynth_intel: Use stringf
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2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/
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2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10
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2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184
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2019-07-07 Dan Ravensloftsynth_intel: Warn about untested Quartus backend
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