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Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-20
diego
Modifications of tests as per Eddie's request
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2020-04-17
diego
Wrong fixed value
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2020-04-16
diego
Adding tests for dynamic part select optimisation
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2020-03-31
Diego H
Replacing log_error for log_file_error due consistency
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2020-03-30
Diego H
Adding error message for when size (width) of number...
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2020-02-06
Diego H
Removing cells_sim.v from bram techmap pass
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2019-12-16
Diego H
Fixing compiler warning/issues. Moving test script...
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2019-12-16
Diego H
Removing fixed attribute value to !ramstyle rules
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2019-12-16
Diego H
Merging attribute rules into a single match block;...
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2019-12-13
Diego H
Refactoring memory attribute matching based on IEEE...
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2019-12-13
Diego H
Renaming BRAM memory tests for the sake of uniformity
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2019-12-12
Diego H
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1...
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2019-12-12
Diego H
Adding a note (TODO) in the memory_params.ys check...
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2019-12-12
Diego H
Updating RAMB36E1 thresholds. Adding test for both...
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2019-12-12
Diego H
Merge https://github.com/YosysHQ/yosys into bram_xilinx
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2019-11-27
Diego H
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
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2019-09-02
Diego H
Updating gowin
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2019-04-13
Diego
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM...
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2019-04-12
Diego
Fixing issues in CycloneV cell sim
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2018-12-04
Diego H
Changes in GoWin synth commands and ALU primitive support
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