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tests: Always print stderr in gem5 Fixtures
2019-12-23
Giacomo Travaglini
tests: Always print stderr in gem5 Fixtures
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-20
Giacomo Travaglini
configs: arm realview(64) regressions using VExpress_GEM5_V1
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-11
Giacomo Travaglini
arch-arm: Always initialize SVE memData
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-11
Giacomo Travaglini
arch-arm: Avoid creating an empty byteEnable vector
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-11
Giacomo Travaglini
cpu: Replace empty byteEnable check with Request::isMasked
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-11
Giacomo Travaglini
cpu: Fix coding style (byteEnable->byte_enable)
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-11
Giacomo Travaglini
cpu: Add byteEnable assertions to readMem and initateMemRead
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-10
Giacomo Travaglini
arch-arm: Disambuiguate NumFloatV7ArchRegs usage
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-10
Giacomo Travaglini
arch-arm: Unify VLdmStm behaviour when reg out of index
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-10
Giacomo Travaglini
arch-arm: Fix NumVecV7ArchRegs value (64->16)
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-10
Giacomo Travaglini
arch-arm: Reorder arch/arm/registers.hh constants
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-10
Giacomo Travaglini
arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-09
Giacomo Travaglini
tests: AArch64 Linux as quick regressions (instead...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-09
Giacomo Travaglini
mem: Add Request::isMasked to check for byte strobing
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-09
Giacomo Travaglini
mem: Add byteEnable copy to Request copy constructor
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-12-03
Giacomo Travaglini
sim-se: Avoid function overloading for syscall implementation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-27
Giacomo Travaglini
base, python: Allow dirname selection for the interpreter
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-27
Giacomo Travaglini
configs: Add --redirects for syscall emulation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-27
Giacomo Travaglini
base: Fix DPRINTF_UNCONDITIONAL on gem5.fast
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2019-11-27
Giacomo Travaglini
configs: Add root redirect path in SE mode only when set
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-27
Giacomo Travaglini
sim-se: Check Path redirection when mmapping
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-27
Giacomo Travaglini
configs: Fix baremetal platform
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-26
Giacomo Travaglini
arch-arm: Make the Tarmac parsed registers case insensitive
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-25
Giacomo Travaglini
dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-21
Giacomo Travaglini
base: Remove tests making use of Big/LittleEndianOrder...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-18
Giacomo Travaglini
arch-arm: Fix short descriptors cacheability during...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-18
Giacomo Travaglini
arch-arm: Fix long descriptors cacheability during...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-14
Giacomo Travaglini
tests: Specify a non-default root folder for regressions
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-12
Giacomo Travaglini
tests: Using super in arm_generic whenever possible
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-12
Giacomo Travaglini
tests: Using super for calling superclass __init__
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-12
Giacomo Travaglini
tests: Remove Noncoherent cache from regressions
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-11
Giacomo Travaglini
arch-arm: Fix TarmacParser handling of 64bit LD/ST
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-11
Giacomo Travaglini
arch-arm: Provide SVE support to the TarmacTracer
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-05
Giacomo Travaglini
arch-arm: Annotate original address in CMOs
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-11-01
Giacomo Travaglini
dev-arm: Add SMMUv3 to VExpress_GEM5_V*
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-31
Giacomo Travaglini
configs: Add baremetal.py example script
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-30
Giacomo Travaglini
base: Name segments after their index
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-22
Giacomo Travaglini
configs: Clean setupBootLoader signature
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-22
Giacomo Travaglini
configs: Do not assume bootmem is a System child
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-22
Giacomo Travaglini
dev-arm, configs: Using _on_chip_memory for on chip...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-16
Giacomo Travaglini
base: Using scoped string in DPRINTFNR
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-16
Giacomo Travaglini
base: Fix gem5.fast compilation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-15
Giacomo Travaglini
dev-arm: Carve out a portion of VExpress_GEM5 for the...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-15
Giacomo Travaglini
configs: Add simpleSystem helper to generate devices...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-10
Giacomo Travaglini
arch-arm: Move generateDtb to ArmSystem
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-10
Giacomo Travaglini
dev-arm, configs: Remove RealViewPBX platform
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-03
Giacomo Travaglini
arch-arm: Annotate CM flag in AA64 CM Instructions
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-03
Giacomo Travaglini
arch-arm: Set CM bit in DataAbort
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-02
Giacomo Travaglini
sim: Mark System::getThreadContext method as const
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-10-02
Giacomo Travaglini
arch-arm: Create helper for sending events (SEV)
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-19
Giacomo Travaglini
dev-arm: Conditionally enable HDLcd when doing DTB...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-19
Giacomo Travaglini
dev-arm: Add HDLcd DTB autogeneration
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-19
Giacomo Travaglini
arch-arm: PSTATE.PAN changes should inval cached regs...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-18
Giacomo Travaglini
arch-arm: Fix Data Abort ISS when caused by Atomic...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-18
Giacomo Travaglini
arch-arm: ISV bit in DataAbort should check for translation...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-18
Giacomo Travaglini
arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-16
Giacomo Travaglini
dev-arm: Allow IOMMU binding to HDLcd
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-13
Giacomo Travaglini
dev-arm: Store the IOMMU reference from within the...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-13
Giacomo Travaglini
dev: Enable DTB IOMMU binding with a DMA object
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Reset HPPI when clearing an LPI
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Add resetHppi method in the GICv3 cpu interface
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Cleanup GICv3 initialization
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Initialize GICD_TYPER once at construction...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Writes to IGRPEN1_EL3 triggering update
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Fix GICv3 ITS cmdq wrapping
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-09
Giacomo Travaglini
dev-arm: Implement message-based SPIs
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-07
Giacomo Travaglini
dev-arm: Add GICD_SGIR register
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev: Enable Terminal output's dump to stdout
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: State update when setting MISCREG_ICC_IGRPENx...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
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2019-09-06
Giacomo Travaglini
dev-arm: Add read/writeBanked helpers to GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: Add explicit AArch64 MiscReg banking
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: Use same template across all MSR inst
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Add GICv3 unimplemented Hyp Active Priorities...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Allow 32-bit access to GITS_TYPER
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Cpu interface groupEnabled check for global...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Check if INTID group is enabled when reading...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Writing GICD_CTLR should trigger an update
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Rewrite GICv3 update
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Fix GICv3 IGRPMOD writes
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: SGI registers undecoded in AArch32
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-06
Giacomo Travaglini
dev-arm: Fix SGI generation
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-09-05
Giacomo Travaglini
dev-arm: Improper translation slot release in SMMUv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-30
Giacomo Travaglini
arm,kvm: Fix python imports from global namespace
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-26
Giacomo Travaglini
dev-arm: Fix GICv3 ITS indexing error
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-26
Giacomo Travaglini
dev-arm: Fix GITS_BASER initialization/access
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-22
Giacomo Travaglini
dev-arm: Start using GITS_CTLR.quiescent bit
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-22
Giacomo Travaglini
dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
dev-arm: Add redistributor-stride property to GICv3
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Replace occ of opModeToEL(currOpMode/cpsr...
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Replace direct use cpsr.el with currEL helper
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
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2019-08-20
Giacomo Travaglini
arch-arm: Overload currEL helper with CPSR argument
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
commit
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commitdiff
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tree
2019-08-20
Giacomo Travaglini
arch-arm: Rewrite the currEL helper method to use opModeToEL
Signed-off-by:
Giacomo Travaglini
<giacomo.travaglini@arm.com>
commit
|
commitdiff
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tree
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