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tests: Always print stderr in gem5 Fixtures
2019-12-23 Giacomo Travaglinitests: Always print stderr in gem5 Fixtures
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-20 Giacomo Travagliniconfigs: arm realview(64) regressions using VExpress_GEM5_V1
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Always initialize SVE memData
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Avoid creating an empty byteEnable vector
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Replace empty byteEnable check with Request::isMasked
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMemRead
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implementation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase, python: Allow dirname selection for the interpreter
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Add --redirects for syscall emulation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase: Fix DPRINTF_UNCONDITIONAL on gem5.fast
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2019-11-27 Giacomo Travagliniconfigs: Add root redirect path in SE mode only when set
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinisim-se: Check Path redirection when mmapping
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Fix baremetal platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-26 Giacomo Travagliniarch-arm: Make the Tarmac parsed registers case insensitive
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Giacomo Travaglinidev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-21 Giacomo Travaglinibase: Remove tests making use of Big/LittleEndianOrder...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix short descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix long descriptors cacheability during...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-14 Giacomo Travaglinitests: Specify a non-default root folder for regressions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super in arm_generic whenever possible
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super for calling superclass __init__
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Remove Noncoherent cache from regressions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Fix TarmacParser handling of 64bit LD/ST
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Provide SVE support to the TarmacTracer
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-05 Giacomo Travagliniarch-arm: Annotate original address in CMOs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-01 Giacomo Travaglinidev-arm: Add SMMUv3 to VExpress_GEM5_V*
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-31 Giacomo Travagliniconfigs: Add baremetal.py example script
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-30 Giacomo Travaglinibase: Name segments after their index
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Clean setupBootLoader signature
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Do not assume bootmem is a System child
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travaglinidev-arm, configs: Using _on_chip_memory for on chip...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Using scoped string in DPRINTFNR
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Fix gem5.fast compilation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travaglinidev-arm: Carve out a portion of VExpress_GEM5 for the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travagliniconfigs: Add simpleSystem helper to generate devices...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travagliniarch-arm: Move generateDtb to ArmSystem
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travaglinidev-arm, configs: Remove RealViewPBX platform
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Annotate CM flag in AA64 CM Instructions
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Set CM bit in DataAbort
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travaglinisim: Mark System::getThreadContext method as const
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travagliniarch-arm: Create helper for sending events (SEV)
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Conditionally enable HDLcd when doing DTB...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Add HDLcd DTB autogeneration
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travagliniarch-arm: PSTATE.PAN changes should inval cached regs...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: Fix Data Abort ISS when caused by Atomic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: ISV bit in DataAbort should check for translation...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-16 Giacomo Travaglinidev-arm: Allow IOMMU binding to HDLcd
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev-arm: Store the IOMMU reference from within the...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev: Enable DTB IOMMU binding with a DMA object
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Reset HPPI when clearing an LPI
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Add resetHppi method in the GICv3 cpu interface
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Cleanup GICv3 initialization
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Initialize GICD_TYPER once at construction...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Writes to IGRPEN1_EL3 triggering update
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix GICv3 ITS cmdq wrapping
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Implement message-based SPIs
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-07 Giacomo Travaglinidev-arm: Add GICD_SGIR register
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev: Enable Terminal output's dump to stdout
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: State update when setting MISCREG_ICC_IGRPENx...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
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2019-09-06 Giacomo Travaglinidev-arm: Add read/writeBanked helpers to GICv3
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Add explicit AArch64 MiscReg banking
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Use same template across all MSR inst
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: SySDC64 Instructions (CMO) using MiscRegIndex
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Add GICv3 unimplemented Hyp Active Priorities...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Allow 32-bit access to GITS_TYPER
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Cpu interface groupEnabled check for global...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Check if INTID group is enabled when reading...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Writing GICD_CTLR should trigger an update
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Rewrite GICv3 update
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Fix GICv3 IGRPMOD writes
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: SGI registers undecoded in AArch32
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Fix SGI generation
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-05 Giacomo Travaglinidev-arm: Improper translation slot release in SMMUv3
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-30 Giacomo Travagliniarm,kvm: Fix python imports from global namespace
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-26 Giacomo Travaglinidev-arm: Fix GICv3 ITS indexing error
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-26 Giacomo Travaglinidev-arm: Fix GITS_BASER initialization/access
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-22 Giacomo Travaglinidev-arm: Start using GITS_CTLR.quiescent bit
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-22 Giacomo Travaglinidev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-20 Giacomo Travaglinidev-arm: Add redistributor-stride property to GICv3
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-20 Giacomo Travagliniarch-arm: Replace occ of opModeToEL(currOpMode/cpsr...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-20 Giacomo Travagliniarch-arm: Replace direct use cpsr.el with currEL helper
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-20 Giacomo Travagliniarch-arm: Overload currEL helper with CPSR argument
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-08-20 Giacomo Travagliniarch-arm: Rewrite the currEL helper method to use opModeToEL
 ...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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