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Added support for "blackbox" attribute to flatten/techmap
2014-07-17 Clifford WolfAdded support for "blackbox" attribute to flatten/techmap
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2014-07-16 Clifford WolfAdded "inout" ports support to read_liberty
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2014-07-16 Clifford WolfSet blackbox attribute in "read_liberty -lib"
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2014-07-16 Clifford WolfFixed spelling of "direction" in read_liberty messages
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2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
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2014-07-16 Clifford WolfChanged tests/techmap/mem_simple_4x1_map for new $mem...
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2014-07-16 Clifford Wolfimproved opt_reduce for $mem/$memwr WR_EN multiplexers
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2014-07-16 Clifford Wolfchanges in verilog frontend for new $mem/$memwr WR_EN...
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2014-07-16 Clifford WolfChanges to "memory" pass for new $memwr/$mem WR_EN...
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2014-07-16 Clifford WolfUpdated simlib to new $mem/$memwr interface
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2014-07-16 Clifford WolfChanged the $mem/$memwr WR_EN input to a per-data-bit...
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2014-07-16 Clifford WolfAdded note to "make test": use git checkout of iverilog
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2014-07-12 Clifford WolfAdded passing of various options to vhdl2verilog
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2014-07-11 Clifford WolfUse "verilog -sv" to parse .sv files
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2014-07-11 Clifford WolfFixed processing of initial values for block-local...
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2014-07-05 Clifford Wolfnow ignore init attributes on non-register wires in...
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2014-07-02 Clifford Wolffixed parsing of constant with comment between size...
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2014-07-02 Clifford Wolfsmall changes in presentation
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2014-06-29 Clifford WolfTiny fix in presentation
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2014-06-29 Clifford WolfProgress in presentation
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2014-06-28 Clifford WolfAdded links to some liberty files to README
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2014-06-26 Clifford WolfProgress in presentation
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2014-06-25 Clifford WolfFixed handling of mixed real/int ternary expressions
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2014-06-24 Clifford WolfMore found_real-related fixes to AstNode::detectSignWidthWorker
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2014-06-22 Clifford WolfProgress in presentation
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2014-06-21 Clifford WolfLittle steps in realmath test bench
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2014-06-21 Clifford Wolffixed signdness detection for expressions with reals
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2014-06-21 Clifford Wolffixed typo
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2014-06-21 Clifford WolfProgress in presentation
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2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff
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2014-06-17 Clifford WolfAdded test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 Clifford WolfAdded AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 Clifford WolfImproved handling of relational op of real values
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2014-06-16 Clifford WolfLittle steps in realmath test bench
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2014-06-16 Clifford WolfImproved ternary support for real values
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2014-06-16 Clifford WolfUse undef (x/z vs. NaN) rules for real values from...
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2014-06-16 Clifford WolfFixed parsing of TOK_INTEGER (implies TOK_SIGNED)
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2014-06-16 Clifford WolfAdded found_real feature to AstNode::detectSignWidth
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2014-06-15 Clifford WolfAdded more calls to "hierarchy" to README file
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2014-06-15 Clifford WolfRemoved long running tests from tests/simple/realexpr...
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2014-06-15 Clifford WolfAdded tests/realmath to "make test"
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2014-06-15 Clifford WolfImproved AstNode::realAsConst for large numbers
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2014-06-15 Clifford WolfImproved realmath test bench
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2014-06-15 Clifford WolfImproved parsing of large integer constants
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2014-06-15 Clifford WolfImproved AstNode::asReal for large integers
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2014-06-14 Clifford Wolfimproved realmath test bench
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2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors
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2014-06-14 Clifford Wolfprogress in realmath test bench
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2014-06-14 Clifford WolfFixed relational operators for const real expressions
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2014-06-14 Clifford Wolfadded first draft of real math testcase generator
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2014-06-14 Clifford WolfProgress in presentation
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2014-06-14 Clifford WolfAdded %D and %c select commands
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2014-06-14 Clifford WolfAdded support for math functions
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2014-06-14 Clifford WolfAdded realexpr.v test case
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2014-06-14 Clifford WolfAdded handling of real-valued parameters/localparams
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2014-06-14 Clifford WolfImplemented more real arithmetic
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2014-06-14 Clifford WolfImplemented basic real arithmetic
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2014-06-14 Clifford WolfAdded real->int convertion in ast genrtlil
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2014-06-13 Clifford WolfAdded Verilog lexer and parser support for real values
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2014-06-12 Clifford WolfAdded read_verilog -sv options, added support for bit...
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2014-06-08 Clifford WolfNow we are in Yoys 0.3.0+ development
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2014-06-08 Clifford WolfTagging Yosys 0.3.0
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2014-06-08 Clifford WolfUpdated ABC to 7600ffb9340c
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2014-06-07 Clifford Wolfadded tests for new verilog features
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2014-06-07 Clifford Wolffixed cell array handling of positional arguments
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2014-06-07 Clifford WolfAdd support for cell arrays
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2014-06-07 Clifford WolfAdded support for repeat stmt in const functions
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2014-06-06 Clifford Wolffurther improved const function support
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2014-06-06 Clifford Wolfmade the generate..endgenrate keywords optional
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2014-06-06 Clifford Wolfimproved const function support
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2014-06-06 Clifford Wolffix functions with no block (but single statement,...
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2014-06-06 Clifford WolfAdded tests/simple/repwhile.v
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2014-06-06 Clifford Wolfimproved ast simplify of const functions
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2014-06-06 Clifford Wolfadded while and repeat support to verilog parser
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2014-06-04 Clifford WolfImproved error message for options after front-end...
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2014-06-03 Clifford Wolfadded tee cmd
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2014-06-01 Clifford WolfFixed log messages in memory_dff
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2014-05-29 Clifford WolfUpdated ABC to rev fa4404b395f0
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2014-05-29 Clifford WolfMerge pull request #36 from hansiglaser/master
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2014-05-12 Clifford WolfFixed bug in opt_reduce (see vloghammer issue_044)
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2014-05-10 Clifford Wolffixed syntax error in dot file created by "show" command
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2014-05-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
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2014-05-09 Clifford WolfUpdated ABC to 67c84cdd49e4
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2014-05-06 Clifford WolfProgress in presentation
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2014-05-06 Clifford WolfImproved ezsat stand-alone tests
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2014-05-03 Clifford Wolfworkaround for OpenBSD 'stdout' implementation
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2014-05-02 Clifford Wolfworkaround for OpenBSD 'stdin' implementation
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2014-05-02 Clifford WolfMerge pull request #35 from bentley/dox
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2014-04-20 Clifford WolfFixed clang -Wdeprecated-register warnings
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2014-04-20 Clifford WolfReplaced depricated %name-prefix= bison directive
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2014-04-20 Clifford Wolfminisat compile fix
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2014-04-18 Clifford WolfUpdated README
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2014-04-11 Clifford WolfMerge pull request #33 from bentley/dox
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2014-04-05 Clifford WolfMerge pull request #31 from bentley/posix-rm
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2014-04-02 Clifford WolfAdded SIMLIB_NOLUT to simlib.v
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2014-04-02 Clifford WolfAdded SIMLIB_NOSR to simlib.v
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2014-03-31 Clifford WolfAdded support for dlatchsr cells
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2014-03-20 Clifford WolfFixed mapping of Verific WIDE_DFFRS operator
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2014-03-20 Clifford WolfFixed mapping of Verific FADD primitive with unconnected...
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2014-03-19 Clifford WolfFixed performance problem in opt_mux with nets driven...
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