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Added support for "blackbox" attribute to flatten/techmap
2014-07-17
Clifford Wolf
Added support for "blackbox" attribute to flatten/techmap
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2014-07-16
Clifford Wolf
Added "inout" ports support to read_liberty
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2014-07-16
Clifford Wolf
Set blackbox attribute in "read_liberty -lib"
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2014-07-16
Clifford Wolf
Fixed spelling of "direction" in read_liberty messages
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2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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2014-07-16
Clifford Wolf
Changed tests/techmap/mem_simple_4x1_map for new $mem...
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2014-07-16
Clifford Wolf
improved opt_reduce for $mem/$memwr WR_EN multiplexers
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2014-07-16
Clifford Wolf
changes in verilog frontend for new $mem/$memwr WR_EN...
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2014-07-16
Clifford Wolf
Changes to "memory" pass for new $memwr/$mem WR_EN...
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2014-07-16
Clifford Wolf
Updated simlib to new $mem/$memwr interface
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2014-07-16
Clifford Wolf
Changed the $mem/$memwr WR_EN input to a per-data-bit...
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2014-07-16
Clifford Wolf
Added note to "make test": use git checkout of iverilog
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2014-07-12
Clifford Wolf
Added passing of various options to vhdl2verilog
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2014-07-11
Clifford Wolf
Use "verilog -sv" to parse .sv files
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2014-07-11
Clifford Wolf
Fixed processing of initial values for block-local...
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2014-07-05
Clifford Wolf
now ignore init attributes on non-register wires in...
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2014-07-02
Clifford Wolf
fixed parsing of constant with comment between size...
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2014-07-02
Clifford Wolf
small changes in presentation
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2014-06-29
Clifford Wolf
Tiny fix in presentation
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2014-06-29
Clifford Wolf
Progress in presentation
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2014-06-28
Clifford Wolf
Added links to some liberty files to README
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2014-06-26
Clifford Wolf
Progress in presentation
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2014-06-25
Clifford Wolf
Fixed handling of mixed real/int ternary expressions
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2014-06-24
Clifford Wolf
More found_real-related fixes to AstNode::detectSignWidthWorker
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2014-06-22
Clifford Wolf
Progress in presentation
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2014-06-21
Clifford Wolf
Little steps in realmath test bench
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2014-06-21
Clifford Wolf
fixed signdness detection for expressions with reals
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2014-06-21
Clifford Wolf
fixed typo
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2014-06-21
Clifford Wolf
Progress in presentation
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2014-06-19
Clifford Wolf
Do not create $dffsr cells with no-op resets in proc_dff
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2014-06-17
Clifford Wolf
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17
Clifford Wolf
Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17
Clifford Wolf
Improved handling of relational op of real values
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2014-06-16
Clifford Wolf
Little steps in realmath test bench
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2014-06-16
Clifford Wolf
Improved ternary support for real values
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2014-06-16
Clifford Wolf
Use undef (x/z vs. NaN) rules for real values from...
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2014-06-16
Clifford Wolf
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
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2014-06-16
Clifford Wolf
Added found_real feature to AstNode::detectSignWidth
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2014-06-15
Clifford Wolf
Added more calls to "hierarchy" to README file
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2014-06-15
Clifford Wolf
Removed long running tests from tests/simple/realexpr...
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2014-06-15
Clifford Wolf
Added tests/realmath to "make test"
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2014-06-15
Clifford Wolf
Improved AstNode::realAsConst for large numbers
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2014-06-15
Clifford Wolf
Improved realmath test bench
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2014-06-15
Clifford Wolf
Improved parsing of large integer constants
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2014-06-15
Clifford Wolf
Improved AstNode::asReal for large integers
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2014-06-14
Clifford Wolf
improved realmath test bench
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2014-06-14
Clifford Wolf
improved (fixed) conversion of real values to bit vectors
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2014-06-14
Clifford Wolf
progress in realmath test bench
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2014-06-14
Clifford Wolf
Fixed relational operators for const real expressions
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2014-06-14
Clifford Wolf
added first draft of real math testcase generator
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2014-06-14
Clifford Wolf
Progress in presentation
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2014-06-14
Clifford Wolf
Added %D and %c select commands
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2014-06-14
Clifford Wolf
Added support for math functions
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2014-06-14
Clifford Wolf
Added realexpr.v test case
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2014-06-14
Clifford Wolf
Added handling of real-valued parameters/localparams
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2014-06-14
Clifford Wolf
Implemented more real arithmetic
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2014-06-14
Clifford Wolf
Implemented basic real arithmetic
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2014-06-14
Clifford Wolf
Added real->int convertion in ast genrtlil
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2014-06-13
Clifford Wolf
Added Verilog lexer and parser support for real values
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2014-06-12
Clifford Wolf
Added read_verilog -sv options, added support for bit...
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2014-06-08
Clifford Wolf
Now we are in Yoys 0.3.0+ development
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2014-06-08
Clifford Wolf
Tagging Yosys 0.3.0
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2014-06-08
Clifford Wolf
Updated ABC to 7600ffb9340c
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2014-06-07
Clifford Wolf
added tests for new verilog features
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2014-06-07
Clifford Wolf
fixed cell array handling of positional arguments
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2014-06-07
Clifford Wolf
Add support for cell arrays
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2014-06-07
Clifford Wolf
Added support for repeat stmt in const functions
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2014-06-06
Clifford Wolf
further improved const function support
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2014-06-06
Clifford Wolf
made the generate..endgenrate keywords optional
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2014-06-06
Clifford Wolf
improved const function support
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2014-06-06
Clifford Wolf
fix functions with no block (but single statement,...
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2014-06-06
Clifford Wolf
Added tests/simple/repwhile.v
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2014-06-06
Clifford Wolf
improved ast simplify of const functions
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2014-06-06
Clifford Wolf
added while and repeat support to verilog parser
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2014-06-04
Clifford Wolf
Improved error message for options after front-end...
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2014-06-03
Clifford Wolf
added tee cmd
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2014-06-01
Clifford Wolf
Fixed log messages in memory_dff
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2014-05-29
Clifford Wolf
Updated ABC to rev fa4404b395f0
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2014-05-29
Clifford Wolf
Merge pull request #36 from hansiglaser/master
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2014-05-12
Clifford Wolf
Fixed bug in opt_reduce (see vloghammer issue_044)
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2014-05-10
Clifford Wolf
fixed syntax error in dot file created by "show" command
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2014-05-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-05-09
Clifford Wolf
Updated ABC to 67c84cdd49e4
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2014-05-06
Clifford Wolf
Progress in presentation
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2014-05-06
Clifford Wolf
Improved ezsat stand-alone tests
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2014-05-03
Clifford Wolf
workaround for OpenBSD 'stdout' implementation
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2014-05-02
Clifford Wolf
workaround for OpenBSD 'stdin' implementation
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2014-05-02
Clifford Wolf
Merge pull request #35 from bentley/dox
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2014-04-20
Clifford Wolf
Fixed clang -Wdeprecated-register warnings
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2014-04-20
Clifford Wolf
Replaced depricated %name-prefix= bison directive
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2014-04-20
Clifford Wolf
minisat compile fix
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2014-04-18
Clifford Wolf
Updated README
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2014-04-11
Clifford Wolf
Merge pull request #33 from bentley/dox
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2014-04-05
Clifford Wolf
Merge pull request #31 from bentley/posix-rm
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2014-04-02
Clifford Wolf
Added SIMLIB_NOLUT to simlib.v
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2014-04-02
Clifford Wolf
Added SIMLIB_NOSR to simlib.v
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2014-03-31
Clifford Wolf
Added support for dlatchsr cells
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2014-03-20
Clifford Wolf
Fixed mapping of Verific WIDE_DFFRS operator
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2014-03-20
Clifford Wolf
Fixed mapping of Verific FADD primitive with unconnected...
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2014-03-19
Clifford Wolf
Fixed performance problem in opt_mux with nets driven...
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